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general description the max11014/max11015 set and control bias condi- tions for dual mesfet power devices found in point-to- point communication and other microwave base stations. the max11014 integrates complete dual ana- log closed-loop drain-current controllers for class a mesfet amplifier operation, while the max11015 tar- gets class ab operation. both devices integrate sram lookup tables (luts) that can be used to store temper- ature and drain-current compensation data. each device includes dual high-side current-sense amplifiers to monitor the mesfet drain currents through the voltage drop across the sense resistors in the 0 to 625mv range. external diode-connected transistors mon- itor the mesfet temperatures while an internal tempera- ture sensor measures the local die temperature of the max11014/max11015. the internal dac sets the volt- ages across the current-sense resistors by controlling the gate voltages. the internal 12-bit sar adc digitizes internal and external temperature, internal dac voltages, current-sense amplifier voltages, and external gate volt- ages. two of the 11 adc channels are available as gen- eral-purpose analog inputs for analog system monitoring. the max11014? gate-drive amplifier functions as an integrator for the class a drain-current control loop while the max11015? gate-drive amplifier functions with a gain of -2 for class ab applications. the current- limited gate-drive amplifier can be fast clamped to an external voltage independent of the digital input from the serial interface. both the max11014 and the max11015 include self-calibration modes to minimize error over time, temperature, and supply voltage. the max11014/max11015 feature an internal reference and can operate from separate adc and dac external references. the internal reference provides a well-regu- lated, low-noise +2.5v reference for the adc, dac, and temperature sensors. these integrated circuits operate from a 4-wire 20mhz spi-/microwire-compatible or 3.4mhz i 2 c*-compatible serial interface (pin-selec- table). both devices operate from a +4.75v to +5.25v analog supply (2.8ma typical supply current), a +2.7v to +5.25v digital supply (1.5ma typical supply current), and a -4.5v to -5.5v negative supply (1.1ma supply current). the max11014/max11015 are available in a 48-pin thin qfn package specified over the -40? to +105? temperature range. * purchase of i 2 c components from maxim integrated products, inc. or one of its sublicensed associated companies, conveys a license under the phillips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by phillips. features ? dual drain-current-sense gain amplifier preset gain of 4 ?.5% accuracy for sense voltages between 75mv and 625mv (max11014) ? common-mode sense-resistor voltage range 0.5v to 11v (max11014) 5v to 32v (max11015) ? low-noise output gate bias with ?0ma gate drive ? fast clamp and power-on reset ? 12-bit dac controls mesfet gate voltage ? internal temperature sensor/dual remote diode temperature sensors ? internal 12-bit adc measures temperature and voltage ? pin-selectable serial interface 3.4mhz i 2 c-compatible interface 20mhz spi-/microwire-compatible interface max11014/max11015 automatic rf mesfet amplifier drain-current controllers ________________________________________________________________ maxim integrated products 1 part pin-package pkg code amplifier max11014 bgtm+ 48 thin qfn-ep** t4877-6 class a max11015 bgtm+* 48 thin qfn-ep** t4877-6 class ab ordering information applications 19-3985; rev 0; 2/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. + denotes a lead-free package. * future product?ontact factory for availability. ** ep = exposed pad. note: all devices are specified over the -40c to +105? operating temperature range. pin configuration and typical operating circuit appear at end of data sheet. cellular base-station rf mesfet bias controllers point-to-point or point-to-multipoint links industrial process control
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v gatevss = v avss = -5.5v to -4.75v, v avdd = +4.75v to +5.25v, v dvdd = +2.7v to v avdd , external v refadc = +2.5v, external v refdac = +2.5v, c refadc = c refdac = 0.1?, v opsafe1 = v opsafe2 = 0, v rcs1+ = v rcs2+ = +5v, c filt1 = c filt3 = 1nf, c filt2 = c filt4 = 1nf, v agnd = v dgnd = 0, v adcin0 = v adcin1 = 0, v aclamp1 = v aclamp2 = -5v, t j = t min to t max , unless otherwise noted. all typical values are at t j = +25?.) parameter symbol conditions min typ max units current-sense amplifier (note 1) max11014 0.5 11.0 common-mode input voltage range v rcs+ max11015 5 32 v 0.5v < v rcs_+ < 11v for the max11014 90 common-mode rejection ratio cmrr 5v < v rcs_+ < 32v for the max11015 90 db i rcs+ 200 input-bias current i rcs- v sense < 100mv over the common-mode range ? ? full-scale sense voltage v sense v sense = v rcs+ - v rcs- 625 mv to within ?.5% accuracy 75 625 to within ?% accuracy 20 625 sense voltage range to within ?0% accuracy 2 625 mv total current set error v sense = 75mv ?.1 ?.5 % current-sense settling time t hscs settles to within ?.5% of final value < 25 ? saturation recovery time settles to within ?.5% accuracy, from v sense = 1.875v < 45 ? class ab input channel untrimmed offset 19 bits offset temperature coefficient 0 bits/ o c gain 4 gain error 0.1 % av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v av ss to agnd ...........................................................-0.3v to -6v rcs1+, rcs1-, rcs2+, rcs2- to gatev ss (max11014) ........................................................-0.3v to +13v rcs1+, rcs1-, rcs2+, rcs2- to agnd (max11015) ........................................................-0.3v to +34v rcs1- to rcs1+.......................................................-6v to +0.3v rcs2- to rcs2+.......................................................-6v to +0.3v gatev ss to agnd...................................................+0.3v to -6v gate1, gate2 to agnd .....(gatev ss - 0.3v) to (av dd + 0.3v) dv dd to av dd ..........................................-0.3v to (av dd + 0.3v) all other analog inputs to agnd ............-0.3v to (av dd + 0.3v) pgaout1, pgaout2 to agnd ..............-0.3v to (av dd + 0.3v) sclk/scl, din/sda, cs /a0, n.c./a2, cnvst , opsafe1, opsafe2 to dgnd.............................-0.3v to (dv dd + 0.3v) dout/a1, spi/ i2c , alarm, busy to dgnd ..............................................-0.3v to (dv dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 48-pin thin qfn (derate 27.0mw/? above +70?)..........................................................2162.2mw operating temperature range .........................-40? to +105? storage temperature range ...............................-60? to 150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300?
max11014/max11015 automatic rf mesfet amplifier drain-current controllers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units class ab output channel untrimmed offset (note 1) 50 ? offset temperature coefficient 0 mv/ o c gain -2 gain error 0.1 % gate-drive amplifier/integrator i gate = -1ma v gatevss + 1 v i gate = +1ma -0.15 -4 mv i gate = -10ma v gatevss + 1.2 v output gate-drive voltage range (note 2) v gate i gate = +10ma -1 -20 mv gate voltage settling time max11015 t gate s ettl es to w i thi n ? 0.5% of fi nal val ue, r s = 50 , c gat e = 15?, see gate o utp ut resi stance vs. gate v ol tag e i n the typ i cal o p er ati ng c har acter i sti cs 1.1 ms no series resistance, r s = 0 0 0.5 output capacitive load (note 3) c gate r s = 500 0 15,000 nf gate voltage noise rms noise, 1khz to 1mhz 250 nv/ hz t c v sc c i sc s 2 s switch on- resistance r opsw clamp gate1 to aclamp1, gate2 to aclamp2 (note 4) 3.6 k adc dc accuracy resolution 12 bits differential nonlinearity dnl adc no missing codes ? lsb integral nonlinearity inl adc (note 5) ?.25 lsb offset error ? ? lsb gain error (note 6) ? ? lsb gain temperature coefficient ?.4 ppm/ o c offset temperature coefficient ?.4 ppm/ o c channel-to-channel offset matching ?.1 lsb channel-to-channel gain matching ?.1 lsb electrical characteristics (continued) (v gatevss = v avss = -5.5v to -4.75v, v avdd = +4.75v to +5.25v, v dvdd = +2.7v to v avdd , external v refadc = +2.5v, external v refdac = +2.5v, c refadc = c refdac = 0.1?, v opsafe1 = v opsafe2 = 0, v rcs1+ = v rcs2+ = +5v, c filt1 = c filt3 = 1nf, c filt2 = c filt4 = 1nf, v agnd = v dgnd = 0, v adcin0 = v adcin1 = 0, v aclamp1 = v aclamp2 = -5v, t j = t min to t max , unless otherwise noted. all typical values are at t j = +25?.)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units adc dynamic accuracy (1khz sine-wave input, -0.5db from full scale, 94.4ksps) signal-to-noise plus distortion sinad 70 db total harmonic distortion thd up to the 5th harmonic -84 db spurious-free dynamic range sfdr 86 db intermodulation distortion imd f in1 = 9.9khz, f in2 = 10.2khz 76 db full-power bandwidth -3db point 1 mhz full-linear bandwidth s / (n + d) > 68db 100 khz adc conversion rate external reference 0.8 power-up time t pu internal reference 50 ? gate_ and sense voltage measurements 40 acquisition time (note 3) t acq all other measurements 1.5 ? conversion time t conv internally clocked 6.5 ? aperture delay 30 ns adcin1, adcin2 inputs input range v adcin_ relative to agnd (note 7) 0 v refadc v input leakage current v adcin_ = 0v or v avdd ?.01 ? ? input capacitance c adcin_ 34 pf temperature measurements t j = +25? ?.25 t j = -40? to +85? (note 3) ?.0 ?.5 internal sensor measurement error t j = -40? to +105? (note 3) ?.0 ?.5 ? t j = +25? ?.0 external sensor measurement error (note 8) t j = -40? to +105? ? ? temperature resolution 0.125 ?/lsb external diode drive 3.26 75.00 ? external temperature sensor drive current ratio 16.6 internal reference reference output voltage v refadc = v refdac +2.490 +2.500 +2.510 v reference output temperature coefficient ?5 ppm/ o c reference output impedance 6.5 k power-supply rejection ratio psrr v avdd = +5v ?% -83 db electrical characteristics (continued) (v gatevss = v avss = -5.5v to -4.75v, v avdd = +4.75v to +5.25v, v dvdd = +2.7v to v avdd , external v refadc = +2.5v, external v refdac = +2.5v, c refadc = c refdac = 0.1?, v opsafe1 = v opsafe2 = 0, v rcs1+ = v rcs2+ = +5v, c filt1 = c filt3 = 1nf, c filt2 = c filt4 = 1nf, v agnd = v dgnd = 0, v adcin0 = v adcin1 = 0, v aclamp1 = v aclamp2 = -5v, t j = t min to t max , unless otherwise noted. all typical values are at t j = +25?.)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units external references refadc input voltage range v refadc +1.0 v avdd v v refadc = +2.5v, f sample = 178ksps 60 refadc input current i refadc acquisition/between conversions ?.01 ? refdac input voltage range v refdac +0.50 +2.52 v refdac input current 26 ? dac dc accuracy resolution 12 bits integral nonlinearity inl dac measured at filt_ ? lsb differential nonlinearity dnl dac measured at filt_, guaranteed monotonic ?.4 ? lsb power supplies analog supply voltage v avdd +4.75 +5.25 v digital supply voltage v dvdd +2.7 av dd v negative supply voltage v gatevss , v avss v gatevss = v avss -5.50 -4.75 v analog supply current i avdd v avdd = +5.25v 2.8 5 ma digital supply current i dvdd v dvdd = +5.25v 1.5 5 ma negative supply current i gatevss + i avss v gatevss = v avss = -5.5v 1.1 1.7 ma analog shutdown current v avdd = +5.25v 0.8 ? digital shutdown current v dvdd = +5.25v 0.2 ? negative shutdown current v gatevss = v avss = -5.5v 0.6 ? serial-interface supplies v il 0.3 x dv dd input voltage v ih 0.7 x dv dd v input hysteresis v hys 0.05 x dv dd v output low voltage v ol busy: i sink = 0.5ma; dout, alarm: i sink = 3ma 0.4 v output high voltage v oh spi/ i2c = dv dd ; busy: i source = 0.5ma; dout, alarm: i source = 2ma dv dd - 0.5v v input current i in ?.01 ?0 ? input capacitance c in 5pf electrical characteristics (continued) (v gatevss = v avss = -5.5v to -4.75v, v avdd = +4.75v to +5.25v, v dvdd = +2.7v to v avdd , external v refadc = +2.5v, external v refdac = +2.5v, c refadc = c refdac = 0.1?, v opsafe1 = v opsafe2 = 0, v rcs1+ = v rcs2+ = +5v, c filt1 = c filt3 = 1nf, c filt2 = c filt4 = 1nf, v agnd = v dgnd = 0, v adcin0 = v adcin1 = 0, v aclamp1 = v aclamp2 = -5v, t j = t min to t max , unless otherwise noted. all typical values are at t j = +25?.)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 6 _______________________________________________________________________________________ spi-interface timing characteristics (note 9) (see figure 1.) i 2 c-interface slow-/fast-mode timing characteristics (note 9) (see figure 2.) parameter symbol conditions min typ max units sclk clock period t cp 40 ns sclk high time t ch 16 ns sclk low time t cl 16 ns din to sclk rise setup time t ds 10 ns din to sclk rise hold time t dh 0ns sclk fall to dout transition t do c l = 30pf 20 ns cs fall to dout enable t dv c l = 30pf (note 3) 40 ns cs rise to dout disable t tr c l = 30pf (note 10) 40 ns cs rise or fall to sclk rise t css 10 ns cs pulse-width high t csw (note 3) 40 ns last sclk rise to cs rise t csh (note 3) 0 ns parameter symbol conditions min typ max units scl clock frequency f scl 0 400 khz bus free time between a stop and start condition t buf 1.3 ? hold time (repeated) for start condition t hd ; sta after this period, the first clock pulse is generated 0.6 ? setup time for a repeated start condition t su ; sta 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? data setup time t su ; dat 100 ns data hold time t hd ; dat (note 11) 0 0.9 ? sda, scl rise time, receiving t r (notes 3, 12) 0 300 ns sda, scl fall time, receiving t f (notes 3, 12) 0 300 ns sda fall time, transmitting t f (notes 3, 12, 13) 20 + 0.1 x c b 250 ns setup time for stop condition t su ; sto 0.6 ? capacitive load for each bus line c b (notes 3, 14) 400 pf pulse width of spikes suppressed by the input filter t sp (note 15) 50 ns
max11014/max11015 automatic rf mesfet amplifier drain-current controllers _______________________________________________________________________________________ 7 i 2 c-wire-interface high-speed-mode timing characteristics (note 9) (see figure 3.) c b = 100pf max c b = 400pf parameter symbol conditions min max min max units serial clock frequency f scl 0 3.4 0 1.7 mhz setup time (repeated) start condition t su ; sta 160 160 ns hold time (repeated) start condition t hd ; sta 160 160 ns scl pulse-width low t low 160 320 ns scl pulse-width high t high 60 120 ns data setup time t su ; dat 10 10 ns data hold time t hd ; dat (note 11) 0 70 0 150 ns scl rise time t rcl (note 3) 10 40 20 80 ns scl rise time, after a repeated start condition and after an acknowledge bit t rcl1 (note 3) 10 80 20 160 ns scl fall time t fcl (note 3) 10 40 20 80 ns sda rise time t rda (note 3) 10 80 20 160 ns sda fall time t fda (note 3) 10 80 20 160 ns setup time for stop condition t su ; sto 160 160 ns capacitive load for each bus line c b (note 14) 100 400 pf pulse width of spikes suppressed by the input filter t sp (note 15) 0 10 0 10 ns
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 8 _______________________________________________________________________________________ miscellaneous timing characteristics parameter symbol conditions min typ max units minimum time to wait after a write command before reading back data from the same location t rdbk (note 16) 1 s cnvst active-low pulse width in adc clock mode 01 t cnv01 (note 3) 20 ns cnvst active-low pulse width in adc clock mode 11 to initiate a temperature conversion t cnv11 (note 3) 20 ns cnvst active-low pulse width in adc clock mode 11 for adcin1/2 acquisition t acq11a (note 3) 1.5 ? adc power-up time (external reference) t apuext 0.8 ? adc power-up time (internal reference) t apuint 50 ? dac power-up time (external reference) t dpuext 2s dac power-up time (internal reference) t dpuint 50 ? acquisition time (internally timed in adc clock modes 00 or 01) t acq 0.6 ? conversion time (internally clocked) t conv 6.5 ? delay to start of conversion time t convw (note 17) 1 s temperature conversion time (internally clocked) t convt 30 ?
max11014/max11015 automatic rf mesfet amplifier drain-current controllers _______________________________________________________________________________________ 9 note 1: all current-sense amplifier specifications are tested after a current-sense calibration (valid when drain current = 0ma). see rcs error vs. gate current in the typical operating characteristics . the calibration is valid only at one temperature and supply voltage and must be repeated if either the temperature or supply voltage changes. note 2: the hardware configuration register? ch_ocm1 and ch_ocm0 bits are set to 0. see table 10a. the max specification is limited by tester limitations. note 3: guaranteed by design. not production tested. note 4: at power-on reset, the output safe switch is closed. see the almhcfg (read/write) section. note 5: integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset err ors have been calibrated out. note 6: offset nulled. note 7: absolute range for analog inputs is from 0 to v avdd . note 8: device and sensor at the same temperature. verified by the current ratio (see the temperature measurements section). note 9: all timing specifications referred to v ih or v il levels. note 10: d out goes into tri-state mode after the cs rising edge. keep cs low long enough for the dout value to be sampled before it goes to tri-state. note 11: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 12: t r and t f measured between 0.3 x dv dd and 0.7 x dv dd . note 13: c b = total capacitance of one bus line in pf. for bus loads between 100pf and 400pf, the timing parameters should be linearly interpolated. note 14: an appropriate bus pullup resistance must be selected depending on board capacitance. for more information, refer to the i 2 c documentation on the philips website. note 15: input filters on the sda and scl inputs suppress noise spikes less than 50ns. note 16: when a command is written to the serial interface, it is passed to the internal oscillator clock to be executed. there is a small synchronization delay before the new value is written to the appropriate register. if the user attempts to read the new value back before t rdbk , no harm will be caused to the data, but the read command may not yet show the new value. note 17: this is the minimum time from the end of a command before cnvst should be asserted. the time allows for the data from the preceding write to arrive and set up the chip in preparation for the cnvst . the time need only be observed when the write affects the adc controls. failure to observe this time may lead to incorrect conversions (for example, conversion of the wrong adc channel). miscellaneous timing characteristics (continued)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 10 ______________________________________________________________________________________ t hd;dat sda scl t rcl1 t rcl t rcl1 t fda sr s r t low t low t high t high t fcl t rda p t hd;sta t su;dat s r = repeated start, p = stop t su;sta t su;sto figure 3. high-speed timing diagram t css sclk t dh t dv t ds cs din dout c7 c6 d1 d0 t ch t csh t css t csw t cl t cp t do t tr figure 1. spi serial-interface timing diagram sda scl t su;sto t r t sp t hd;sta t su;sta t f t high t su;dat t hd;dat t r t hd;sta t f s s s r p s = start, s r = repeated start, p = stop t low t buf figure 2. slow-/fast-speed timing diagram
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 11 8 6 4 2 0 2.5 4.0 3.0 3.5 4.5 5.0 5.5 digital supply current vs. digital supply voltage max11014 toc01 dv dd supply voltage (v) dv dd supply current (ma) av dd = 5.25v 2.40 2.41 2.43 2.42 2.44 2.45 analog supply current vs. analog supply voltage max11014 toc02 av dd supply voltage (v) av dd supply current (ma) 4.750 5.000 4.875 5.125 5.250 -0.4 -0.2 0 0.2 0.4 rcs error vs. temperature max11014 toc03 temperature ( c) rcs error (mv) -50 25 50 -25 0 75 100 125 after calibration before calibration 40 s/div -5v max11014 toc04 v gate 1v/div gate voltage power-up 0 200 100 400 300 500 600 0500 filt1/filt3 settling time vs. filt1/filt3 capacitive load max11014 toc05 capacitive load (pf) settling time ( s) 200 100 300 400 10% to 90% t rise t fall 0.50 0.25 0 -0.25 -0.50 -10 0 -5 5 10 rcs error vs. gate current max11014 toc06 gate current (ma) rcs error (mv) sourcing sinking 20 15 10 5 0 -5 -3 -4 -2 -1 0 max11014 toc07 v gate (v) gate output resistance ( ) gatev ss = av ss = -5v gate output resistance vs. gate voltage 1 s/div filt1 1mv/div ac-coupled max11014 toc08 glitch impulse -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 dac integral nonlinearity vs. ouput code max11014 toc09 output code dac inl (lsb) typical operating characteristics (v gatevss = -5.5v; v avdd = v dvdd = +5v, gatev ss = av ss = -5v, external v refadc = +2.5v; external v refdac = +2.5v; c ref = 0.1?; t a = t min to t max , unless otherwise noted.)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 12 ______________________________________________________________________________________ typical operating characteristics (continued) (v gatevss = -5.5v; v avdd = v dvdd = +5v, gatev ss = av ss = -5v, external v refadc = +2.5v; external v refdac = +2.5v; c ref = 0.1?; t a = t min to t max , unless otherwise noted.) -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 dac differtial nonlinearity vs. output code max11014 toc10 output code dac dnl (lsb) -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 adc integral nonlinearity vs. output code max11014 toc11 output code adc inl (lsb) -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 1024 2048 3072 4096 adc differential nonlinearity vs. output code max11014 toc12 output code adc dnl (lsb) 60 70 65 75 80 0.1 10 1 100 1000 adc sinad vs. frequency max11014 toc13 frequency (khz) sinad (db) 50 60 80 70 90 100 0.1 10 1 100 1000 adc sfdr vs. frequency max11014 toc14 frequency (khz) sfdr (db) 0.001 0.01 0.1 0.1 10 1 100 1000 adc total harmonic distortion vs. frequency max11014 toc15 frequency (khz) thd (%) -120 -80 -100 -40 -60 -20 0 050 adc fft plot max11014 toc16 analog input frequency (khz) amplitude (db) 20 10 30 40 f analog_in = 9.982khz f clk = 3.052mhz sinad = 71.28dbc snr = 71.51dbc thd = -84.18dbc sfdr = -86.94dbc 3 4 6 5 7 8 0.1 10 1 100 1000 digital supply current vs. sampling rate max11014 toc17 sampling rate (ksps) dv dd supply current (ma) av dd = dv dd = 5v 2.5026 2.5024 2.5022 2.5020 2.5018 4.750 5.000 4.875 5.125 5.250 adc internal reference voltage vs. supply voltage max11014 toc18 supply voltage (v) adc reference voltage (v) av dd = dv dd
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 13 2.5018 2.5016 2.5014 2.5012 2.5010 4.750 5.000 4.875 5.125 5.250 dac internal reference voltage vs. supply voltage max11014 toc19 supply voltage (v) dac reference voltage (v) av dd = dv dd 2.48 2.49 2.50 2.51 2.52 internal reference voltage vs. temperature max11014 toc20 temperature ( c) reference voltage (v) -50 25 50 -25 0 75 100 125 v refdac v refadc 2.0 1.5 1.0 0.5 0 4.750 5.000 4.875 5.125 5.250 adc offset error vs. analog supply voltage max11014 toc21 av dd (v) adc offset error (lsb) 0 1 2 3 4 adc offset error vs. temperature max11014 toc22 temperature ( c) adc offset error (lsb) -50 25 50 -25 0 75 100 125 0 1.0 0.5 2.0 1.5 2.5 3.0 4.750 5.000 4.875 5.125 5.250 adc gain error vs. analog supply voltage max11014 toc23 av dd (v) adc gain error (lsb) -3 -1 -2 1 0 3 2 4 -50 0 25 -25 50 75 100 125 adc gain eror vs. temperature max11014 toc24 temperature ( c) adc gain error (lsb) internal temperature sensor error vs. temperature max11014 toc25 -1.00 -0.75 -0.25 -0.50 0.50 0.75 0.25 0 1.00 internal temperature sensor error ( c) -50 0 25 -25 50 75 100 125 temperature ( c) gnd v rcs1- 100mv/div v pgaout1 200mv/div v filt1 200mv/div 0 to 100mv v sense transient response max11014 toc26 10ms/div gnd gnd v rcs1- 200mv/div v pgaout1 500mv/div v filt1 500mv/div 0 to 250mv v sense transient response max11014 toc27 10ms/div typical operating characteristics (continued) (v gatevss = -5.5v; v avdd = v dvdd = +5v, gatev ss = av ss = -5v, external v refadc = +2.5v; external v refdac = +2.5v; c ref = 0.1?; t a = t min to t max , unless otherwise noted.)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 14 ______________________________________________________________________________________ pin description pin name function 1 din/sda serial data input. data is latched into the serial interface on the rising edge of sclk in spi mode. connect a pullup resistor to sda in i 2 c mode. 2 dout/a1 serial data output in spi mode/address select 1 in i 2 c mode. data transitions on the falling edge of sclk. dout is high impedance when cs is high. connect a1 to dv dd or dgnd to set the device address to i 2 c mode. 3 adcin1 analog input 1 4 adcin2 analog input 2 5 dxn1 remote-diode current sink. connect the emitter of a base-emitter junction remote npn transistor to dxn1. 6 dxp1 remote-diode current source. connect dxp1 to the base/collector of a remote temperature-sensing npn transistor. do not leave dxp1 open ; connect to dxn1 if no remote diode is used. 7 dxn2 remote-diode current sink. connect the emitter of a base-emitter junction remote npn transistor to dxn2. 8 dxp2 remote-diode current source. connect dxp2 to the base/collector of a remote temperature-sensing npn transistor. do not leave dxp2 open ; connect to dxn2 if no remote diode is used. 9 refdac dac reference input/output. connect a 0.1? capacitor to agnd in external reference mode. see the hcfg (read/write) section. 10 refadc adc reference input/output. connect a 0.1? capacitor to agnd in external reference mode. see the hcfg (read/write) section. 11, 27 av dd positive analog supply voltage. set av dd between +4.75v and +5.25v. bypass with a 1? and a 0.1? capacitor in parallel to agnd. 12, 26 agnd analog ground 13 aclamp2 mesfet2 external clamping voltage input 14 gate2 mesfet2 gate connection. see the gate-drive amplifiers section. 15 gatev ss gate-drive amplifier negative power-supply input. set gatev ss between -4.75v and -5.5v. connect externally to av ss . bypass with a 1? and a 0.1? capacitor in parallel to agnd. 16, 28, 29, 34?7 n.c. no connection. not internally connected. 17 aclamp1 mesfet1 external clamping voltage input 18 gate1 mesfet1 gate connection. see the gate-drive amplifiers section. 19 filt1 channel 1 filter 1 input. see figures 5 and 6. 20 filt2 channel 1 filter 2 input. see figures 5 and 6. 21 filt3 channel 2 filter 3 input. see figures 5 and 6. 22 filt4 channel 2 filter 4 input. see figures 5 and 6. 23 pgaout1 channel 1 amplifier voltage output. see the pgaout outputs section and figures 5 and 6. 24 pgaout2 channel 2 amplifier voltage output. see the pgaout outputs section and figures 5 and 6. 25 av ss negative analog supply voltage. set av ss between -4.75v and -5.5v. connect externally to gatev ss . bypass with a 1? and a 0.1? capacitor in parallel to agnd.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 15 pin description (continued) pin name function 30 rcs2+ channel 2 current-sense-resistor connection. connect to the external supply powering channel 2? mesfet drain, in the range of +0.5v to +11v (max11014) or +5v to +32v (max11015). bypass with a 1? and a 0.1? capacitor in parallel to agnd. if unused, connect to rcs1+. 31 rcs2- channel 2 current-sense-resistor connection. connect to the channel 2 mesfet drain. decouple as required by the application. if unused, connect to rcs2+. 32 rcs1- channel 1 current-sense-resistor connection. connect to the channel 1 mesfet drain. decouple as required by the application. if unused, connect to rcs1+. 33 rcs1+ channel 1 current-sense-resistor connection. connect to the external supply powering channel 1? mesfet drain, in the range of +0.5v to +11v (max11014) or +5v to +32v (max11015). bypass with a 1? and a 0.1? capacitor in parallel to agnd. if unused, connect to rcs2+. 38 opsafe1 operating safe channel 1 input. set opsafe1 high to clamp gate1 to aclamp1 for fast protection of enhancement fet power transistors. 39 opsafe2 operating safe channel 2 input. set opsafe2 high to clamp gate2 to aclamp2 for fast protection of enhancement fet power transistors. 40 busy busy output. busy asserts high under certain conditions when the device is busy. see the busy output section. 41 dv dd digital supply voltage. set dv dd between +2.7v and av dd . bypass with a 1? and a 0.1? capacitor in parallel to dgnd. 42 dgnd digital ground 43 cnvst active-low conversion start input. set cnvst low to begin a conversion in clock modes 01 and 11. connect cnvst to dv dd when issuing conversion commands through the serial interface. 44 alarm alarm output. alarm asserts when the temperature or voltage measurements exceed their preset high or low thresholds. 45 cs /a0 chip-select input in spi mode/address select 0 in i 2 c mode. cs is an active-low input. when cs is low, the serial interface is enabled. when cs is high, dout is high impedance. connect a0 to dv dd or dgnd to set the device address in i 2 c mode. 46 spi/ i2c spi-/i 2 c-interface select input. connect spi/ i2c to dv dd to select spi mode. connect spi/ i2c to dgnd to select i 2 c mode. 47 n.c./a2 no connection in spi mode/address select 2 in i 2 c mode. connect a2 to dv dd or dgnd to set the device address in i 2 c mode. 48 sclk/scl serial clock input. clocks data in and out of the serial interface. (duty cycle must be 40% to 60%.) connect a pullup resistor to scl in i 2 c mode. see table 10 for details on programming the clock mode. ?p exposed pad. connect to agnd and a large copper plane to meet power dissipation specifications. do not use as a ground connection.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 16 ______________________________________________________________________________________ detailed description the max11014/max11015 set and monitor the bias con- ditions for dual mesfet power devices found in cellular base stations and point-to-point microwave links. the internal dac sets the voltage across the current-sense resistor by controlling the gate voltage. these devices integrate a 12-bit adc to measure voltage, internal and external temperature, and communicate through a 4-wire 20mhz spi-/microwire-compatible serial interface or 2-wire 3.4mhz i 2 c-compatible serial interface (pin-selectable). the max11014/max11015 operate from an internal +2.5v reference or individual adc and dac external references. the external current-sense resistors moni- tor voltages over the 0 to (v dacref / 4) range. two cur- rent-sense amplifiers with a preset gain of four monitor the voltage across the sense resistors. the max11014/max11015 accurately measure their inter- nal die temperature and two external remote diode tem- perature sensors. the remote pn junctions are typically the base-emitter junction of an npn transistor, either discrete or integrated on a cpu, fpga, or asic. the max11014/max11015 also feature an alarm output that can be triggered during an internal or external overtemperature condition, an excessive current-sense voltage, or an excessive gate voltage. figure 4 shows the max11014? functional diagram. the max11014 integrates complete dual analog closed-loop drain-current controllers for class a mesfet amplifier operation. see the max11014 class a control loop section. the analog control loop sets the drain current through the current-sense resistors. the mesfet gate-drive amplifier can vary the dac code accordingly if the temperature or other system variables change. implement class a amplifier operation with the follow- ing three steps: 1) characterization characterize the mesfet over temperature to deter- mine the amplifier? set of drain-current values, assuming the part-to-part calibration curve is consis- tent. there may be an offset shift, but no important change in the shape of the function. load these val- ues into the max11014 luts at power-up. in opera- tion, there is a linear interpolation between the values stored in the luts. adjust the drain current for other variables such as output power or drain voltage by loading values into the numerical k luts. 2) calibration in production of the power amplifier, measure the quiescent drain current at a fixed calibration temper- ature (probably room) and adjust the v set(code) value until the drain current is within the specified limits for that temperature. the v set(code) value is stored for loading after power-up. prior to operation, command a pga calibration after powering up by writing to the pga calibration control register, setting the track bit to 0 and the docal bit to 1 (see table 18). 3) operation upon request, the max11014 measures the temper- ature of the mesfet and compares it with the previ- ous reading. if the temperature reading has changed, the max11014 reads the luts with the characterization data and updates the dac to cor- rect the drain current. setting the track, docal, and selftime bits to 1 in the pga calibration con- trol register starts automatic monitoring and adjust- ment of drain current for variations in temperature. also, if the k luts are used, their values are monitored for changes. a dac correction is then made if necessary. for class ab operation with the max11015, measure the mesfet temperature and set the gate_ voltage through the luts and dac to control the drain current. see the max11015 class ab control section. implement class ab amplifier operation with the same three steps as class a operation, with the exception that the luts set the gate_ voltage for constant drain current with varying temperature. power-on reset on power-up, the max11014/max11015 are in full power-down mode (see the shut (write) section). to change to normal power mode, write two commands to the shutdown register. set the fullpd bit to 0 (other bits in the shutdown register are ignored) on the first command. a second command to this register then activates the internal blocks. max11014 class a control loop the max11014 is designed to set and continuously control the drain current for mesfet power amplifiers configured to operate in class a. set the dac code to control the voltage across the rcs_+ and rcs_- cur- rent-sense resistor connections. the max11014 inter- nal control loop automatically keeps the voltage across the current-sense resistor to the value set by the dac. see the 12-bit dac section.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 17 refadc mux internal temperature sensor internal +2.5v reference por conversion, scan, oscillator, and control voltage/temperature digital comparator adcin1 bias current generator drain supply drain supply sclk/scl din/sda cs/a0 dout/a1 cnvst busy power good dv dd dgnd gatev ss gate1 rcs1+ reset register map aclamp1 digital control 12-bit dac code filt1 filt2 rcs1- 12-bit register gate2 rcs2+ aclamp2 filt3 filt4 rcs2- 12-bit register alarm alarm limit alarm sense voltage control dac channel select adc channel select dac control adc control serial in terface 48-entry interpolating temperature sram lut 48-entry interpolating k sram lut 48-entry interpolating temperature sram lut 48-entry interpolating k sram lut alu adcin2 dxp1 dxn1 dxp2 dxn2 12-bit adc refdac agnd av dd av ss pgaout1 pgaout2 channel 1 channel 2 opsafe1 opsafe2 channel 1 dac channel 2 dac d g s d g s n.c./a2 spi/i2c external temperature sensor processing max11014 max11015 figure 4. functional diagram
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 18 ______________________________________________________________________________________ once the control loop has been set, the max11014 automatically maintains the drain-current value. figure 5 details the amplifiers that bias the channel 1 and channel 2 control loops. the dual current-sense amplifiers amplify the voltage between rcs_+ and rcs_- by four and add an offset voltage (+12mv nominally). these current-sense ampli- fiers amplify sense voltages between 0 and 625mv when v refdac = +2.5v. see the current-sense amplifiers section. the current-sense amplifier output injects a scaled-down replica of the mesfet drain current at the summing node to complete the internal analog feedback loop. the summing node drives the gate-drive amplifier through a 100k series resistor. the gate-drive amplifier is config- ured as an integrator by the external capacitor connect- ed between gate1/gate2 and filt2/filt4. the gate-drive amplifier includes automatic offset cancella- tion between 0 and 24mv to null the 12mv offset from the current-sense amplifier. see the register descriptions and pgacal (write) sections. the max11014? analog control loop setpoint is described by the following equation: where: v filt (code = 000h) = v filt1 (channel 1) and v filt3 (channel 2) when the thrudac1/thrudac2 register code is set to 000h. v filt = v filt1 (channel 1) and v filt3 (channel 2). v rcs+ - v rcs- = the voltage drop across the current- sense resistor. connect a capacitor from filt2 to gate1 to form an integrator (setting the control-loop dominant pole) with the channel 1 internal 100k resistor. connect a capacitor from filt4 to gate2 to form an integrator (setting the control-loop dominant pole) with the chan- nel 2 internal 100k resistor. the gate-drive amplifier? output drives the mesfet gates. see the gate-drive amplifiers section. the channel 1 dac voltage is output to filt1 through a series 580k resistor. the channel 2 dac voltage is output to filt3 through a series 580k resistor. connect a capacitor from filt1 to agnd and filt3 to agnd to set the filter? time constant for the respective channel. max11015 class ab control the max11015 is designed to be used with a class ab amplifier configuration to independently measure the drain current and set the gate_ output voltages through the serial interface. after sensing the drain current with no rf signal applied, set the dac code to obtain the desired gate_ voltage. figure 6 details the amplifiers that bias the channel 1 and channel 2 control. the max11015 internal 12-bit dac voltage is applied to the gate-drive amplifier, which has a preset gain of -2. see the gate-drive amplifiers section. setting the dac code between fffh and 000h typically produces a gate_ voltage between 0 and (-2 x v refdac ). see the hcfg (read/write) section for details on adjusting the gate_ maximum voltage. the channel 1 dac voltage is output to filt1 through a series 580k resistor. the channel 2 dac voltage is output to filt3 through a series 580k resistor. connect a capacitor from filt1 to agnd and filt3 to agnd to set the filter? time constant for the respective channel. connect filt2 and filt4 to agnd (max11015 only). the dual current-sense amplifiers amplify the voltage between rcs_+ and rcs_- by four and add an offset voltage (+12mv nominally). the current-sense ampli- fiers amplify sense voltages between 0 and 625mv when v refdac = +2.5v. see the current-sense amplifiers section. current-sense amplifiers the dual current-sense amplifiers amplify the voltage between rcs_+ and rcs_- and add an offset voltage. connect a resistor between rcs_+ and rcs_- to sense the mesfet drain current. the current-sense amplifiers scale the sense voltage by four. these amplifiers also reject the drain supply voltage that appears as a dc common-mode level on the current signal. the gate-drive amplifier includes automatic offset can- cellation between 0 and 24mv to null the 12mv offset from the current-sense amplifier. see the pgacal (write) section. gate-drive amplifiers the gate-drive amplifiers control the mesfet gate bias settings. the max11014? channel 1 and channel 2 dac voltages are routed through a summing node and into the gate-drive amplifiers. the max11015? channel 1 and channel 2 dac voltages are routed directly to the gate-drive amplifiers, which have a preset gain of -2. see the 12-bit dac section for details on setting the dac codes. vv v code h v rcs rcs filt filt +? ?= =? () 000 4
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 19 figure 5. max11014 class a analog control loop max11014 + + gate1 filt2 power mesfet +0.5v to +11v rcs1+ rcs1- channel 1 dac filt1 serial interface pgaout1 channel 1 adc gate-drive amplifier 580k cs /a0 sclk/scl din/sda dout/a1 c filt1 100k c filt2 gate2 filt4 power mesfet +0.5v to +11v rcs2+ rcs2- channel 2 dac filt3 pgaout2 channel 2 adc current-sense amplifier current-sense amplifier gate-drive amplifier 580k c filt3 100k c filt4 n.c./a2
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 20 ______________________________________________________________________________________ max11015 gate1 filt2 power mesfet +5v to +32v rcs1+ rcs1- channel 1 dac filt1 serial interface pgaout1 channel 1 adc current-sense amplifier gate-drive amplifier gate-drive amplifier 580k gain = -2 gate2 filt4 power mesfet +5v to +32v rcs2+ rcs2- channel 2 dac filt3 pgaout2 channel 2 adc current-sense amplifier 580k gain = -2 c filt3 c filt1 cs /a0 sclk/scl din/sda dout/a1 n.c./a2 figure 6. max11015 class ab analog control
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 21 connect the mesfet drain to the rcs_- input. connect the mesfet? gate to the gate_ output. set the gate_ voltage to -2 x v refdac to turn the mesfet fully off. set the gate_ voltage to 0v to turn the mesfet fully on. see figure 7. the max11014/max11015 gate_ output voltage can be clamped to the external voltage applied at aclamp_. setting opsafe_ high clamps the gate_ voltage unconditionally. the gate_ can also be clamped by different commands issued through the serial interface. these devices can also monitor the alarms through the software to modify the clamping mechanism. see the automatic gate clamping and almhcfg (read/write) sections. 12-bit adc description the max11014/max11015 adcs use a fully differential successive-approximation register (sar) conversion technique and on-chip track-and-hold (t/h) circuitry to convert temperature and voltage signals into 12-bit dig- ital results. the analog inputs accept single-ended input signals. single-ended signals are converted using a unipolar transfer function. see the adc transfer function section for more details. the internal adc block converts the results of the inter- nal die temperature, remote diode temperature read- ings, current-sense voltages, and adcin_ voltages. the adc block also reads back the gate_ analog out- put voltage and converts it to a 12-bit digital result. the conversion results are written to the fifo memory. the fifo holds up to 15 words (each word of 16 bits) with a leading 4-bit channel tag to indicate which channel the 12-bit data comes from. see table 25. the fifo reads back data words either one at a time or continuously. see the adccon (write) section. the fifo always stores the most recent conversion results and allows the oldest data to be overwritten. the fifo indicates an overflow condition and underflow condition (read of an empty fifo) through the flag register. see the flag (read) section. analog input track and hold the equivalent circuit of figure 8 details the max11014/max11015? adcin_ input architecture. in track mode, a positive input capacitor is connected to adcin1/adcin2. a negative input capacitor is con- nected to agnd. after the t/h enters hold mode, the difference between the sampled input voltages and agnd is converted. the input-capacitance charging rate determines the time required for the t/h to acquire an input signal. the required acquisition time lengthens with the increase of the input signal? source imped- ance. any source impedance below 300 does not significantly affect the adc? ac performance. a high- impedance source can be accommodated either by placing a 1? capacitor between adcin_ and agnd. the combination of the analog-input source impedance and the capacitance at the analog input creates an rc filter that limits the analog-input bandwidth. mesfet fully on off gate voltage gate voltage alarm thresholds adc code read from the fifo 0v -2 x v refdac fffh 000h default v h = fffh default v l = 000h v gate within thresholds too high too low new high gate voltage alarm threshold new low gate voltage alarm threshold user entered dac code fffh 000h rcs_+ to rcs_- sense voltage pgaout voltage 0mv v refdac / 4 v refdac 0v figure 7. dac code range
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 22 ______________________________________________________________________________________ analog input protection internal esd protection diodes clamp adcin1/adcin2 to av dd and agnd, allowing them to swing from (agnd - 0.3v) to (av dd + 0.3v) without damage. however, for accurate conversions near full scale, the inputs must not exceed av dd by more than 50mv or be lower than agnd by 50mv. if an analog input voltage exceeds the supplies, limit the input current to 2ma. temperature measurements the max11014/max11015 measure their internal die temperature and two external remote-diode tempera- tures. write to the adc conversion register to com- mand a temperature conversion. see table 19. set the ch6 bit to 1 to calculate the remote-diode dxp2/dxn2 temperature sensor reading and load the data into the fifo. set the ch1 bit to 1 to calculate the remote-diode dxp1/dxn1 temperature-sensor reading and load the data into the fifo. set the ch0 bit to 1 to calculate the internal die temperature-sensor reading and load the data into the fifo. temperature data is output in signed two?-complement format at dout in spi mode and sda in i 2 c mode. see figure 22 for the tempera- ture transfer function. the max11014/max11015 perform internal tempera- ture measurements with a diode-connected transistor. the diode bias current changes from 66? to 4? to produce a temperature-dependent bias voltage differ- ence. the second conversion result at 4? is subtract- ed from the first at 66? to calculate a digital value that is proportional to absolute temperature. the stored data result is the above digital code minus an offset to adjust from kelvin to celsius. the reference voltage for the temperature measurements is derived from the internal reference source to ensure the temperature calibration of 1 lsb corresponding to +0.125?. for external temperature readings, connect an npn transistor between dxp_ and dxn_. connect the base and collector together as shown in figure 4 to form a base-emitter pn junction. the max11014/max11015 feature an alarm output that trips when the internal or external temperature rises above an upper threshold value or drops below a lower threshold value. set the high and low temperature thresholds through the chan- nel 1/channel 2 high/low temperature alarm threshold registers. see tables 3, 4, and 5. the temperature-sensing circuits power up for the first temperature measurement in an adc conversion scan. the temperature-sensing block remains on until the end of the scan to avoid an additional 50? power-up delay for each individual temperature channel. see the adccon (write) section, figure 31, and figure 32. the temperature-sensor circuits remain powered up when adcin1, adcin2 agnd hold hold hold av dd / 2 comparator dac refadc agnd cin+ cin- acq acq acq figure 8. adc equivalent input circuit
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 23 the adc conversion register? continuous convert bit (conconv) is set to 1 and the current adc conver- sion includes a temperature channel. the temperature- sensor circuits remain powered up until the conconv bit is set low. the external temperature sensor drive current ratio has been optimized for a 2n3904 npn transistor with an ide- ality factor of 1.0065. the nonideality offset is removed internally by a preset digital coefficient. using a transis- tor with a different ideality factor produces a proportion- ate difference in the absolute measured temperature. for more details on this topic and others related to using an external temperature sensor, see application note 1057 compensating for ideality factor and series resistance differences between thermal-sense diodes ?and application note 1944 temperature monitoring using the max1253/54 and max1153/54 on maxim? website: www.maxim-ic.com. 12-bit dac the max11014/max11015 include two voltage-output, 12-bit monotonic dacs with ? lsb integral nonlineari- ty error and ?.4 lsb differential nonlinearity error. the dac operates from the internal +2.5v reference or an external reference voltage supplied at refdac. when using an external voltage reference, bypass refdac with a 0.1? capacitor to agnd. the refdac external voltage range is +0.7v to +2.5v. the max11014? channel 1/channel 2 dacs set the sense voltage between rcs_+ and rcs_- by control- ling the gate_ bias. see the max11014 class a control loop section. the max11015? channel 1/chan- nel 2 dacs drive the gate_ outputs directly, indepen- dent of the current-sense voltages, through the gate-drive amplifier with a gain of -2. see the max11015 class ab control section. set the channel 1/channel 2 dac code by writing to the respective channel? dac input registers, dac input and output registers, or v set registers. write to the dac input registers (table 16) and use a subsequent write to the software load dac register (table 21) to control the timing of the update. write to the dac input and output registers (table 17) to set the dac output voltage code directly, independent of the software load dac register bits. write to the v set registers (table 14) to include lut data in the dac code. writing to the v set registers triggers a v dac(code) calculation as shown in the following equation: where v dac(code) = the modified channel1/channel 2 12-bit dac code. v set(code) = the 12-bit dac code written to the chan- nel 1/channel 2 v set registers. lut k [k] = the interpolated, fractional 12-bit k lut value. the k lut data is derived from a variety of sources, including: the v set register value, the k para- meter register value, or various adc channels. see the sram luts section. lut temp [temp] = the interpolated, fractional 12-bit two?-complement temperature lut value. the tempera- ture lut data is derived from either internal or external temperature values. see the sram luts section. the v dac(code) equation code is then loaded into the dac input register or dac output register, depending on the corresponding channel? ldac bit in the soft- ware configuration register. see table 11. self-calibration calibrate channel 1 and channel 2 by writing to the pga calibration control register. the max11014/max11015 function after power-up without a calibration. however, for best performance after pow- ering up, command a calibration by setting the track bit to 0 and the docal bit to 1 (see table 18). subsequently, set the track, docal, and selftime bits to 1 to minimize loss of performance over tempera- ture and supply voltage. the self-calibration algorithm cancels offsets at the gate-drive amplifier inputs in approximately 95? incre- ments to improve accuracy. the self-calibration routine can be commanded when the dacs are powered down, but the results will not be accurate. for best results, run the calibration after the dac power-up time, t dpuext . the adc? operation is suspended during a self-calibration. the end of the self-calibration routine is indicated by the busy output returning low. see the busy output section. wait until the end of the self-cali- bration routine before requesting an adc conversion. v v lut k x lut temp dac code set code k temp () () ( [ ] [ ]) ==+ 1
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 24 ______________________________________________________________________________________ adc/dac references the max11014/max11015 provide an internal low- noise +2.5v reference for the adcs, dacs, and tem- perature sensors. set bits d3?0 within the hardware configuration register to control the source of the dac and adc references. see tables 10c and 10d. connect a voltage source to refadc between +1.0v and av dd in external adc reference mode. connect a voltage source to refdac between +0.7v to +2.5v in external dac reference mode. when using an external voltage reference, bypass refadc and refdac with 0.1? capacitors to agnd. power supplies the max11014/max11015 operate from separate ana- log and digital power supplies. set the analog supply voltage, av dd , between +4.75v and +5.25v. set the digital supply voltage, dv dd , between +2.7v and av dd . bypass av dd with a 0.1? and 1? capacitor to agnd and dv dd with a 0.1? and 1? capacitor to dgnd. the analog circuitry typically consumes 2.8ma of supply current and the digital circuitry 3.7ma. set the negative analog supply voltages, av ss and gatev ss , between -4.75v and -5.5v. connect av ss and gatev ss together externally. bypass each of these neg- ative supplies with a 0.1? and 1? capacitor to agnd. the rcs_+ inputs supply the power to the input section of the current-sense amplifiers. set rcs_+ between +0.5v and +11v on the max11014 and +5v to +32v on the max11015. bypass rcs_+ with a 0.1? and 1? capacitor to agnd. serial interface the max11014/max11015 feature a pin-selectable i 2 c/spi serial interface. connect spi/ i2c to gnd to select i 2 c mode, or connect spi/ i2c to v dd to select spi mode. sda and scl (i 2 c mode) and din, sclk, and cs (spi mode) facilitate communication between the max11014/max11015 and the master. spi compatibility (spi/ i2c = dv dd ) the max11014/max11015 communicate through a ser- ial interface, compatible with spi and microwire devices. for spi, ensure that the spi bus master (typi- cally a ?) runs in master mode so it generates the ser- ial clock signal. set the sclk frequency to 20mhz or less, and set the clock polarity (cpol) and phase (cpha) in the ? control registers to the same value. the max11014/max11015 operate with sclk idling high or low, and thus operate with cpol = cpha = 0 or cpol = cpha = 1. set cs low to latch input data at din on the rising edge of sclk. output data at dout is updated on the falling edge of sclk. see figure 1. temperature values are available in signed two?-com- plement format, while all others are in straight binary. a high-to-low transition on cs initiates the 24-bit data input cycle. once cs is low, write an 8-bit command byte (msb first) at din to indicate which internal regis- ter is being accessed. the command byte also identi- fies whether the data to follow is to be written into the serial interface or read out. see the register descriptions section. after writing the command byte, write two data bytes at din or read two data bytes at dout. keep cs low throughout the entire 24-bit word write. the serial-interface circuitry is common to the adc and dac sections. when writing data, write an 8-bit command word and 16 data bits at din. see figure 9. data is input to the serial interface on the rising edge of sclk. when read- ing data, write an 8-bit command byte at din and read the following 16 data bits at dout. see figure 10. data transitions at dout on the falling edge of sclk. din can be set high or low while data is being transferred out at dout.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 25 c6 cs sclk din 123456 78910 2324 c7 (msb) c5 c4 c3 c2 c1 c0 (lsb) d15 (msb) d14 d1 d0 (lsb) the command byte initializes the internal registers. the next 16 bits are data bits. figure 9. max11014/max11015 write timing c6 cs sclk din 1234 56 789 10 23 24 c7 (msb) c5 c4 c3 c2 c1 c0 (lsb) d15 (msb) d14 d1 d0 (lsb) the command byte initializes the internal registers. the next 16 data bits are read out. dout x = don't care. note: dout may be driven up to 2 clock cycles before d15 is available. any data on dout before d15 is available, should be ignored. figure 10. max11014/max11015 read timing
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 26 ______________________________________________________________________________________ i 2 c compatibility (spi/ i2c = dgnd) the max11014/max11015 communicate through an i 2 c-compatible 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max11014/max11015 and the master at data rates up to 3.4mhz. the master (typically a ?) initiates data transfer on the bus and generates the scl signal to per- mit data transfer. the max11014/max11015 behave as i 2 c slave devices that transfer and receive data. scl and sda must be pulled high for proper i 2 c oper- ation. this is typically done with pullup resistors (1k or greater). series resistors are optional. the series resis- tors protect the input architecture from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. one data bit transfers during each scl clock cycle. a minimum of 9 bytes is required to transfer a byte in or out of the max11014/max11015 (8 bits and an ack/nack). data is latched in on scl? rising edge and read out on scl? falling edge. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is stable and high are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), a low-to-high transition on sda while scl is high (figure 11). a repeated start condition (sr) can be used in place of a stop condition to leave the bus active and the interface mode unchanged (see the high-speed mode section). the address byte, command byte, and data bytes are transmitted between the start and stop conditions. nine clock cycles are required to transfer the data in or out of the max11014/max11015. see figures 15 and 16. if the receiver returns a not-acknowledge bit (nack), the max11014/max11015 releases the bus. if the not acknowledge occurs in the middle of a 16-bit word, the remaining bits are lost. scl sda sp sr s = start s r = repeated start p = stop figure 11. start and stop conditions
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 27 acknowledge and not-acknowledge conditions data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max11014/max11015 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device pulls sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keeps it low during the high period of the clock pulse (figure 12). to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves sda high during the high period of the clock pulse. monitor the acknowledge bits to detect an unsuccessful data transfer. an unsuccessful data transfer happens if a receiving device is busy or if a system fault occurs. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. slave address the max11014/max11015 have a 7-bit i 2 c slave address. the msbs of the slave address are factory programmed to 0101. the logic state of address inputs a2, a1, and a0 determine the 3 lsbs of the device address (figure 13). connect a2, a1, and a0 to dv dd for a high logic state or dgnd for a low logic state. therefore, a maximum of eight max11014/max11015 devices can be connected on the same bus at one time. the max11014/max11015 continuously wait for a start condition followed by its slave address. when the device recognizes its slave address, it is ready to accept or send data depending on bit 8, the r/ w bit. high-speed mode at power-up, the bus timing is set for fast mode (f/s mode, up to 400khz i 2 c clock), which limits interface speed. switch to high-speed mode (hs mode, up to 3.4mhz i 2 c clock) to increase interface speed. the interface is capable of supporting slow (up to 100khz), fast (up to 400khz), and high-speed (up to 3.4mhz) protocols. see figure 14. scl sda s not acknowledge acknowledge 12 89 figure 12. acknowledge bits 010 a2 1a1a0r/ w a slave address s scl sda 123456789 slave address bits a2, a1, and a0 correspond to the logic state of address-select input pins a2, a1, and a0. figure 13. slave address byte
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 28 ______________________________________________________________________________________ transfer from f/s mode to hs mode by addressing all devices on the bus with the hs-mode master code 0000 1xxx (x = don? care). after successfully receiv- ing the hs-mode master code, the max11014/ max11015 issue a nack, allowing sda to be pulled high for one cycle. after the nack, the max11014/max11015 operate in hs mode. send a repeated start (s r ) followed by a slave address to initiate hs-mode communication. if the master generates a stop condition, the max11014/max11015 return to f/s mode. use a repeated start (s r ) condition in place of a stop (p) condition to leave the bus active and the mode unchanged. command byte/data bytes (write cycle) begin a write cycle by issuing a start condition (through the master), followed by 7 slave address bits (figure 13) and a write bit (r/ w = 0). after writing the 8th bit, the max11014/max11015 (the slave) issue an acknowledge signal by pulling sda low for one clock. write the command byte to the slave after writing the slave address (c7?0, msb first). see figures 15 and 17, table 1, and the command byte section. following the command byte, the slave issues another acknowl- edge signal, pulling sda low for one clock cycle. after the command byte, write 2 data bytes, allowing for two additional acknowledge signals after each byte. the master ends the write cycle by issuing a stop condition. when operating in hs mode, a stop condition returns the bus to f/s mode. see the high-speed mode section. the max11014/max11015? internal conversion clock frequency is 4.8mhz (typ), resulting in a typical conver- sion time of 4.6s. figure 15 shows a complete write cycle. 000 1 0xxx a hs-mode master code scl sda s sr f/s mode hs mode slave to master master to slave s 1 slave address a 711 w command byte 8 p or sr 1 msb determines whether to read or write to registers. 4-byte write cycle number of bits a 1 data byte 8 a 1 data byte 8 a 1 figure 14. f/s-mode to hs-mode transfer figure 15. write cycle
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 29 command byte/data bytes (read cycle) begin a read cycle by issuing a start condition fol- lowed by writing a 7-bit address (figure 18) and a read bit (r/ w = 1). after writing the 8th bit, the max11014/max11015 (the slave) issue an acknowl- edge signal by pulling sda low for one clock cycle. write the command byte to the slave after writing the slave address (c7?0, msb first). see figures 16, 18, 19, table 1, and the command byte section. following the command byte, the slave issues another acknowl- edge signal, pulling sda low for one clock cycle. after writing the command byte, issue a repeated start condition (sr), write the slave address byte again, and write a 9th bit for an acknowledge signal. after a third acknowledge signal, read out the 2 bytes at sda. after reading the first byte, the master should send an acknowledge (a). after reading the second byte, the master should send a not-acknowledge (n) followed by a stop signal. default reads a standard i 2 c read command involves writing the slave address, command byte, slave address byte again, and then reading the data at sda. this is detailed in the 5-byte read cycle sequence in figure 16. read from the max11014/max11015 through the default read command to avoid writing a command byte and second slave address byte. see the default read sequence in figure 16. begin a default read cycle by writing the slave address byte followed by an acknowledge bit. read out the next 2 data bytes, with acknowledge bits from the master to the slave following each byte. continue to acknowledge the data by sending acknowledge (a) signals. after reading the final byte, the master should send a not- acknowledge (n) followed by a stop signal. the default read cycle reads out the data from the register (located in table 2) of the previously assigned command byte. see figure 18. this default read feature is useful for 2- wire reads to maximize the data throughput without having the overhead of setting the slave address and command byte each time. figure 16. read cycle s 1 slave address slave address slave address a 711 r command byte 8 p or sr p or sr 1 msb determines whether to read or write to registers 5-byte read cycle number of bits number of bits asr 1 data byte 8 n 1 data byte 8 n 1 a 711 r 71 r s 1 default read cycle 1 data byte data byte 8 a 18 n 1 a 1 slave to master master to slave
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 30 ______________________________________________________________________________________ scl sda sda direction a6 a5 a4 a3 a2 a1 a0 r/ w ack out in c6 c5 c4 c3 c2 c1 c0 out ack in scl sda sda direction d15 d14 d13 d12 d11 d10 d9 d8 ack out in d7 d6 d5 d4 d3 d2 d1 d0 in ack stop start out in r/ w figure 17. max11014/max11015 i 2 c write timing scl sda d7 d6 d5 d4 d3 d2 d1 d0 nack in out p sda direction scl sda a6 a5 a4 a3 a2 a1 a0 ack out in d15 d14 d13 d12 d11 d10 d9 d8 in ack sr sda direction r/ w scl sda sda direction a6 a5 a4 a3 a2 a1 a0 r/ w ack out in c6 c5 c4 c3 c2 c1 c0 out ack in start r/ w figure 18. max11014/max11015 i 2 c read timing
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 31 command byte begin a write or read to the max11014/max11015 by writing a command byte at din/sda. set bit c7 to 1 for a read operation. set bit c7 to 0 for a write operation. see table 1. the remaining bits, c6?0, determine the register accessed by the command byte. table 2 indi- cates the register? read/write access. c7 is the msb of the command byte and c0 is the lsb. following the command byte, write or read 2 data bytes to/from bits d15?0. d15 is the msb of the 2 data bytes and d0 is the lsb. see figures 9, 10, 17, 18, and 19 and the register descriptions section. scl sda d7 d6 d5 d4 d3 d2 d1 d0 nack in out stop sda direction scl sda sda direction a6 a5 a4 a3 a2 a1 a0 r/ w ack in in c6 c5 c4 c3 c2 c1 c0 ack start r/ w out, data from last read command byte register figure 19. max11014/max11015 i 2 c default read timing 24-bit serial input word command byte data bits msb lsb c7 r/ w c6 c5 c4 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 1. input command bits
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 32 ______________________________________________________________________________________ register descriptions the max11014/max11015 communicate between the internal registers and external bus lines through the serial interface. table 1 details the command bits (c7?0) and the data bits (d15?0) of the serial input word. table 2 details the command byte and the sub- sequent register accessed. tables 3?7 detail the vari- ous read and write internal registers and their power-on reset states. on power-up, the max11014/max11015 are in full power-down mode (see the shut (write) section). to change to normal power mode, write two commands to hex code register description mnemonic write read adc conversion adccon 62 alarm flag register almflag f8 channel 1 dac input ipdac1 48 channel 1 dac input and output thrudac1 4a channel 1 high gate voltage alarm threshold vh1 28 a8 channel 1 high sense voltage alarm threshold ih1 24 a4 channel 1 high temperature alarm threshold th1 20 a0 channel 1 k parameter usrk1 44 channel 1 low gate voltage alarm threshold vl1 2a aa channel 1 low sense voltage alarm threshold il1 26 a6 channel 1 low temperature alarm threshold tl1 22 a2 channel 1 v set vset1 40 channel 2 dac input ipdac2 4c channel 2 dac input and output thrudac2 4e channel 2 high gate voltage alarm threshold vh2 34 b4 channel 2 high sense voltage alarm threshold ih2 30 b0 channel 2 high temperature alarm threshold th2 2c ac channel 2 k parameter usrk2 46 channel 2 low gate voltage alarm threshold vl2 36 b6 channel 2 low sense voltage alarm threshold il2 32 b2 channel 2 low temperature alarm threshold tl2 2e ae channel 2 v set vset2 42 first-in first-out memory fifo 80 flag register flag f6 hardware alarm configuration almhcfg 3c bc hardware configuration hcfg 38 b8 lut address lutadd 7a lut data lutdat 7c fc pga calibration control pgacal 5e shutdown shut 64 software alarm configuration almscfg 3e be software clear sclr 74 software configuration scfg 3a ba software load dac ldac 66 table 2. register listing
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 33 the shutdown register. set the fullpd bit to 0 (other bits in the shutdown register are ignored) on the first command. a second command to this register acti- vates the internal blocks. th1 and th2 (read/write) set the external channel 1 and channel 2 high tempera- ture alarm thresholds by writing command bytes 20h and 2ch, respectively. following the command byte, write 12 bits of data to bits d11?0. read the high tem- perature channel 1 and channel 2 alarm thresholds by writing command bytes a0h and ach, respectively. following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. temper- ature data must be written and read in two?-comple- ment format, with the lsb corresponding to +0.125?. see table 3. the por value of the high temperature alarm threshold registers is 0111 1111 1111, which corresponds to +255.875?. see table 4 for examples of channel 1/channel 2 high and low temperature threshold settings. see figures 25 and 27 for alarm examples. tl1 and tl2 (read/write) set the external channel 1 and channel 2 low tempera- ture alarm thresholds by writing command bytes 22h and 2eh, respectively. following the command byte, write 12 bits of data to bits d11?0. read the low tem- perature channel 1 and channel 2 alarm thresholds by writing command bytes a2h and aeh, respectively. following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. temper- ature data must be written and read in two?-comple- ment format, with the lsb corresponding to +0.125?. see table 5. the por value of the low temperature alarm threshold registers is 1000 0000 0000, which corresponds to -256.0?. see figures 25 and 27 for alarm examples. ih1 and ih2 (read/write) set the channel 1 and channel 2 high sense voltage alarm thresholds by writing command bytes 24h and 30h, respectively. following the command byte, write 12 bits of data to bits d11?0. read the high sense voltage channel 1 and channel 2 alarm thresholds by writing command bytes a4h and b0h, respectively. bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state xxxx011111111111 bit value (c) xxxx msb (sign) 128 64 32 16 8421 0.5 0.25 lsb 0.125 temperature setting data bits d11?0 (two? complement) -40c 1110 1100 0000 -1.625c 1111 1111 0011 0c 0000 0000 0000 +27.125c 0000 1101 1001 +105c 0011 0100 1000 table 3. th1 and th2 (read/write) bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state x xxx100000000000 bit value (c) x xxx msb (sign) 128 64 32 16 8421 0.5 0.25 lsb 0.125 table 5. tl1 and tl2 (read/write) table 4. high/low temperature alarm threshold examples x = don? care. x = don? care.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 34 ______________________________________________________________________________________ following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. sense volt- age data must be written and read in straight binary format. see table 6. the por value of the high sense voltage alarm threshold registers is 1111 1111 1111. see figures 25 and 27 for alarm examples. the sense voltage is measured between rcs_+ and rcs_-. a reading of 1111 1111 1111 corresponds to v refdac / 4. a reading of 0000 0000 0000 corre- sponds to 0mv. il1 and il2 (read/write) set the channel 1 and channel 2 low sense voltage alarm thresholds by writing command bytes 26h and 32h, respectively. following the command byte, write 12 bits of data to bits d11?0. read the low sense volt- age channel 1 and channel 2 alarm thresholds by writing command bytes a6h and b2h, respectively. following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. sense volt- age data must be written and read in straight binary format. see table 7. the por value of the low sense voltage alarm threshold registers is 0000 0000 0000. see figures 25 and 27 for alarm examples. the sense voltage is measured between rcs_+ and rcs_-. a reading of 1111 1111 1111 corresponds to v refdac / 4. a reading of 0000 0000 0000 corre- sponds to 0mv. vh1 and vh2 (read/write) set the channel 1 and channel 2 high gate voltage alarm thresholds by writing command bytes 28h and 34h, respectively. following the command byte, write 12 bits of data to bits d11?0. read the high gate voltage channel 1 and channel 2 alarm thresholds by writing command bytes a8h and b4h, respectively. following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. voltage data must be written and read in straight binary format. see table 8. the por value of the high gate voltage alarm threshold registers is 1111 1111 1111. see figure 7 for a gate voltage example. see figures 25 and 27 for alarm examples. vl1 and vl2 (read/write) set the channel 1 and channel 2 low gate voltage alarm thresholds by writing command bytes 2ah and 36h, respectively. following the command byte, write 12 bits of data to bits d11?0. read the low gate volt- age channel 1 and channel 2 alarm thresholds by writing command bytes aah and b6h, respectively. following the command byte, read 12 bits of data from bits d11?0. bits d15?12 are don? care. voltage data must be written and read in straight binary format. see table 9. the por value of the low gate voltage alarm threshold registers is 0000 0000 0000. see figure 7 for a gate voltage example. see figures 25 and 27 for alarm examples. table 7. il1 and il2 (read/write) bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state xxxx000000000000 bit value xxxx msb lsb table 8. vh1 and vh2 (read/write) bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state xxxx111111111111 bit value xxxx msb lsb table 6. ih1 and ih2 (read/write) bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state xxxx111111111111 bit value xxxx msb lsb x = don? care. x = don? care. x = don? care.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 35 hcfg (read/write) select each channel? maximum gate voltage, clock mode, adc monitoring, dac and adc reference modes by setting bits d10?0 in the hardware configu- ration register. set the command byte to 38h to write to the hardware configuration register. set the command byte to b8h to read from the hardware configuration register. bits d15?11 are don? care. set the ch2ocm1/0 bits, d10 and d9, to determine the maxi- mum positive gate2 output voltage. set the ch1ocm1/0 bits, d8 and d7, to determine the maxi- mum positive gate1 output voltage. see table 10. set the adcmon bit, d6, to 1 to load the adc results into the fifo. set adcmon to 0 to not load adc results into the fifo. set the cksel1/0 bits, d5 and d4, to determine the conversion and acquisition timing clock modes. see table 10b. also, see the internally timed acquisitions and conversions and the externally timed acquisitions and conversions sections. set the adcref1/0 bits, d3 and d2, to determine the adc ref- erence source. see table 10c. set the dacref1/0 bits, d1 and d0, to determine the dac reference source. see table 10d. scfg (read/write) write to the software configuration register to determine whether a v dac(code) calculation value is loaded to the dac input register or dac input and output regis- ter. this register also sets the control modes for the k parameter and temperature lookup values in the v dac(code) calculation. set the command byte to 3ah to write to the software configuration register. set the command byte to bah to read from the software config- uration register. bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset state xxxx000000000000 bit value xxxx msb lsb bit name data bit reset state function x d15?12 x don? care. ch2ocm1 d11 0 ch2ocm0 d10 0 maximum gate2 voltage control bits. ch1ocm1 d9 0 ch1ocm0 d8 0 maximum gate1 voltage control bits. x d7 x don? care. adcmon d6 0 adc monitor bit. set to 1 to load adc results into the fifo. set to 0 to not load any adc results into the fifo. the value of adcmon does not affect whether the results from any particular adc conversion are checked against alarm limits or examined for changes to the v dac(code) equations. cksel1 d5 0 cksel0 d4 0 clock mode and cnvst configuration bits. adcref1 d3 0 adcref0 d2 0 adc reference select bits. dacref1 d1 0 dacref0 d0 0 dac reference select bits. x = don? care. table 9. vl1 and vl2 (read/write) table 10. hcfg (read/write)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 36 ______________________________________________________________________________________ bits d15?12 of the software configuration register are don? care. set the ldac2 bit, d11, to 1 to load the new value of v dac2 , upon completion of a v dac2(code) calculation, into both the channel 2 dac input and out- put registers. see figure 20. set to 0 to load the new value of v dac2 , upon completion of a v dac2(code) calculation, to only the channel 2 dac input register. set the t2comp1/0 bits, d10 and d9, to control the channel 2 temperature lut. see table 11a. set the ksrc2-2/1/0 bits, d8, d7, and d6, to control the chan- nel 2 k parameter lut. see table 11b and the sram luts section. table 10b. clock modes table 10c. adc reference modes table 10a. maximum gate_ voltage modes ch_ocm1 ch_ocm0 function 0 0 maximum positive voltage at gate_ = agnd. 0 1 maximum positive voltage at gate_ = agnd + 250mv. 1 0 maximum positive voltage at gate_ = agnd + 500mv. 1 1 maximum positive voltage at gate_ = agnd + 750mv. cksel1 cksel0 conversion clock acquisition/sampling 0 0 internal internally timed acquisitions and conversions. default state. begin a conversion by writing to the adc conversion register to convert all channels specified in this register. 0 1 internal internally timed acquisitions and conversions. begin a conversion by pulling cnvst low only once for at least 20ns to convert all of the channels selected in the adc conversion register. 1 0 reserved do not use. 1 1 internal externally timed single acquisitions. conversions internally timed. begin each individual conversion by pulling cnvst low for each channel converted. see the electrical characteristics table for cnvst timing. the max11014/max11015 acquire while cnvst is low and sample when cnvst returns high. adcref1 adcref0 adc voltage reference 0 x external. bypass refadc with a 0.1? capacitor to agnd. 10 internal. leave refadc unconnected. 1 1 internal. bypass refadc with a 0.1? capacitor to agnd for better noise performance. table 10d. dac reference modes dacref1 dacref0 dac voltage reference 0 x external. bypass refdac with a 0.1? capacitor to agnd. 10 internal. leave refdac unconnected. 1 1 internal. bypass refdac with a 0.1? capacitor to agnd for better noise performance. x = don? care. x = don? care.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 37 set the ldac1 bit, d5, to 1 to load the new value of v dac1 , upon completion of a v dac1(code) calculation, into both the channel 1 dac input and output registers. set to 0 to load the new value of v dac1 , upon comple- tion of a v dac1(code) calculation, to only the channel 1 dac input register. set the t1comp1/0 bits, d4 and d3, to control the channel 1 temperature lut. see table 11a. set the ksrc1-2/1/0 bits, d2, d1, and d0 to control the channel 1 k parameter lut. see table 11b and the sram luts section. set the channel 1/channel 2 dac code by writing to the respective channel? dac input registers, dac input and output registers, or v set registers. write to the dac input registers (table 16) and use a subsequent write to the software load dac register (table 21) to control the timing of the update. write to the dac input and output registers (table 17) to set the dac output voltage code directly, independent of the software load dac register bits. write to the v set registers (table 14) to include lut data in the dac code. writing to the v set registers triggers a v dac(code) calculation by the following equation: where v dac(code) = the modified channel1/channel 2 12-bit dac code. v set(code) = the 12-bit dac code written to the chan- nel 1/channel 2 v set registers. lut k [k] = the interpolated, fractional 12-bit k lut value. the k lut data is derived from a variety of sources, including the v set register value, the k para- meter register value, or various adc channels. see the sram luts section. lut temp [temp] = the interpolated, fractional 12-bit two?-complement temperature lut value. the tempera- ture lut data is derived from either internal or external temperature values. see the sram luts section. when the ksrc_-2/ksrc_-1/ksrc_-0 bits are set to 000 and t_comp1/t_comp0 bits are set to 00 or 01, the v dac(code) equation simplifies to: note: this is a special case and will not trigger a v gate calculation unless a sample already exists. this functionality should be accessed by the thrudac registers. for temperature samples or sampled klut sources to automatically trigger v dac(code) calculations, the adc must be configured to provide these samples. therefore, the adc conversion register (table 19) must have the relevant channel bits set and the adc must be in a suitable clocking mode, regardless of the adcmon bit setting. vv dac code set code () () = v v lut k x lut temp dac code set code k temp () () ( [ ] [ ]) =+ 1 channel 1/channel 2 dac input registers: channel 1/channel 2 dac input and output registers: (ipdac1/ipdac2 thrudac1/thrudac2) (thrudac1/ thrudac2) channel 1/ channel 2 dac output voltage ldac register v dac calculation ldac_ bits set to 1 in scfg register figure 20. dac register format
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 38 ______________________________________________________________________________________ table 11. scfg (read/write) bit name data bit reset state function x d15?12 x don? care. ldac2 d11 0 channel 2 load dac. set to 1 to load the new value of v dac2(code) , upon completion of a v dac2(code) calculation, into both the channel 2 dac input and output registers. when set to 1, busy pulses high after a new v dac2 output is calculated. set to 0 to load the new value of v dac2(code) , upon completion of a v dac2(code) calculation, to only the channel 2 dac input register. when set to 0, set the dacch2 bit high in the software load dac register to transfer the v dac(code) calculation value from the dac input register to the dac output. t2comp1 d10 0 t2comp0 d9 0 channel 2 temperature lut control bits. ksrc2-2 d8 0 ksrc2-1 d7 0 ksrc2-0 d6 0 channel 2 k lut control bits. ldac1 d5 0 channel 1 load dac. set to 1 to load the new value of v dac1 , upon completion of a v dac1(code) calculation, into both the channel 1 dac input and output registers. when set to 1, busy pulses high after a new v dac1 output is calculated. set to 0 to load the new value of v dac1 , upon completion of a v dac1(code) calculation, to only the channel 1 dac input register. when set to 0, set the dacch1 bit high in the software load dac register to transfer the v dac(code) calculation value from the dac input register to the dac output. t1comp1 d4 0 t1comp0 d3 0 channel 1 temperature lut control bits. ksrc1-2 d2 0 ksrc1-1 d1 0 ksrc1-0 d0 0 channel 1 k lut control bits.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 39 table 11a. channel 1/channel 2 temperature lut control modes table 11b. channel 1/channel 2 k lut control modes ksrc_-2 ksrc_-1 ksrc_-0 function 000 no k lut operations performed. this bit setting simplifies the v dac(code) calculation to: v dac(code) = v set(code) (1 + lut temp [temp]) 001 the v dac(code) calculation simplifies to: v dac(code) = v set(code) (1 + lut k [vset] x lut temp [temp]) 010 the v dac(code) calculation simplifies to: v dac(code) = v set(code) (1 - lut k [usrk] x lut temp [temp]) 011 the v dac(code) calculation simplifies to: v dac(code) = v set(code) (1 + lut k [sense voltage] x lut temp [temp]) 100 the v dac(code) calculation simplifies to: v dac(code) = v set(code) (1 + lut k [adcin_] x lut temp [temp]) 101 the v dac(code) calculation simplifies to: v dac(code) = v set(code) + usrk x lut k [vset] x lut temp [temp] 110 the v dac(code) calculation simplifies to: v dac(code) = v set(code) + usrk x lut k [sense voltage] x lut temp [temp] 111 the v dac(code) calculation simplifies to: v dac(code) = v set(code) + usrk x lut k [adcin_] x lut temp [temp] t_comp1 t_comp0 function 00 a change in temperature does not trigger a v dac(code) calculation. any v dac(code) calculation triggered in another way does not include the temperature lookup. this bit setting simplifies the v dac(code) calculation to v dac(code) = v set(code) (1 + lut k [k]). 01 a change in temperature does not trigger a v dac(code) calculation. any v dac(code) calculation triggered in another way does not include the temperature lookup. this bit setting simplifies the v dac(code) calculation to v dac(code) = v set(code) (1 - lut k [k]). 10 a change in the channel 1/channel 2 external temperature sensor reading triggers a v dac(code) calculation for the corresponding dac channel. when a v dac(code) calculation is triggered, the calculation includes the temperature lookup function. 11 a change in the internal temperature sensor reading triggers a v dac(code) calculation for the corresponding channel. when a v dac(code) calculation is triggered, the calculation includes the temperature lookup function.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 40 ______________________________________________________________________________________ almhcfg (read/write) the hardware alarm configuration register controls the active states of the alarm output. set the com- mand byte to 3ch to write to the hardware alarm con- figuration register. set the command byte to bch to read the hardware alarm configuration register. bits d15?12 are don? care. set the intemp bit, d11, to 1 to cause alarm comparisons for channel 2 to use the internal temperature conversion result. set the almcmp bit, d10, to 1 to set the alarm output in comparator mode. set almcmp to 0 to set the alarm output in interrupt mode. see figure 25. when operating in windowing mode, set the vghyst1/0 bits, d9 and d8, to control the gate_ volt- age alarm hysteresis level. this hysteresis level applies to both channel 1 and channel 2. see table 12a and figure 25. when operating in windowing mode, set the ithyst1/0 bits, d7 and d6, to control the sense voltage and temperature alarm hysteresis level. this hysteresis level applies to both channel 1 and channel 2. see table 12b. set the alm2clmp1/0 bits, d5 and d4, to control whether or not the gate2 output is clamped to the external voltage at aclamp2. see table 12c. set the alm1clmp1/0 bits, d3 and d2, to control whether or not the gate1 output is clamped to the external volt- age at aclamp1. see table 12c and the automatic gate clamping section. set the almpol bit, d1, to 1 make the alarm output active-low. set almpol to 0 to make the alarm output active-high. set the almopn bit, d0, to 1 to make the alarm output an open-drain output. set almopn to 0 to force the alarm output to be push-pull. bit name data bit reset state function x d15?12 x don? care. intemp d11 0 internal temperature conversion bit. set to 1 to cause alarm comparisons for channel 2 to use the internal temperature conversion result. set to 0 to cause alarm comparisons for channel 2 to use the external temperature conversion result. almcmp d10 0 alarm comparator bit. set to 1 to configure the alarm output in comparator mode. set to 0 to configure the alarm output in interrupt mode. vghyst1 d9 0 vghyst0 d8 0 gate voltage hysteresis bits. the vghyst_ bits control the built-in hysteresis level when using the alarm function in windowing mode for gate voltage measurements. the same value is used for the gate voltage alarm measurements in both channels. ithyst1 d7 0 ithyst0 d6 0 sense voltage/temperature hysteresis bits. the ithyst_ bits control the built-in hysteresis level when using the alarm function in windowing mode for sense voltage and temperature measurements. the same value is used for the sense voltage and temperature alarm measurements in both channels. alm2clmp1 d5 0 alm2clmp0 d4 0 channel 2 alarm clamp bits. alm1clmp1 d3 0 alm1clmp0 d2 0 channel 1 alarm clamp bits. almpol d1 0 alarm polarity bit. set to 1 to force the alarm output to be active-low. set to 0 to force the alarm output to be active-high. almopn d0 0 alarm open-drain/push-pull output bit. set to 1 to configure the alarm output as open-drain. an external pullup or pulldown resistor is required. multiple alarm outputs can be wired together onto a single line in open-drain mode. set to 0 to configure the alarm output as a push-pull output (no external resistor required). table 12. almhcfg (read/write)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 41 almscfg (read/write) the software alarm configuration register controls which voltage and temperature channels trigger the alarm output and whether the alarm comparators operate in windowing or hysteresis mode. set the com- mand byte to 3eh to write to the software alarm con- figuration register. set the command byte to beh to read the software alarm configuration register. bits d15?12 are don? care. set the valarm2 bit, d11, to 1 to enable alarm functionality for gate2 voltage mea- surements. set the vwin2 bit, d10, to 1 to monitor the gate2 voltage with the alarm comparator in window- ing mode. set vwin2 to 0 to monitor the gate2 voltage with the alarm comparator in hysteresis mode. set the talarm2 bit, d9, to 1 to enable alarm function- ality for channel 2 temperature measurements. set the twin2 bit, d8, to 1 to monitor the channel 2 tempera- ture with the alarm comparator in windowing mode. set twin2 to 0 to monitor the channel 2 temperature with the alarm comparator in hysteresis mode. set the ialarm2 bit, d7, to 1 to enable alarm functionality for channel 2 sense voltage (rcs2+ to rcs2-) measure- ments. set the iwin2 bit, d6, to 1 to monitor the chan- nel 2 sense voltage with the alarm comparator in windowing mode. set iwin2 to 0 to monitor the channel 2 sense voltage with the alarm comparator in hystere- sis mode. ithyst1 ithyst0 function 0 0 8 lsbs of hysteresis. 0 1 16 lsbs of hysteresis. 1 0 32 lsbs of hysteresis. 1 1 64 lsbs of hysteresis. table 12b. sense voltage/temperature hysteresis levels alm_clmp1 alm_clmp0 function 00 default state. the gate_ outputs are clamped to the respective external voltage applied at aclamp_ independent of alarms. gate_ remains clamped until this register value is changed or a software clear command is issued. 01 the corresponding alarm bit in the alarm flag register goes high if an alarm condition is triggered by a conversion of sense voltage, temperature, or gate_ voltage. however, the gate_ outputs are not clamped. 10 fully automatic clamping. the gate_ outputs are clamped to the respective external voltage applied at aclamp_ when an alarm condition is triggered. the clamp is removed if a subsequent temperature or sense voltage conversion removes the alarm condition. gate_ remains clamped when a gate_ voltage alarm is triggered. for a gate_ voltage alarm, alm_clmp 10 mode functions the same as 11 mode. this exception breaks the feedback loop created by sampling gate_ voltage and then clamping the same signal. 11 semi-automatic clamping. the gate_ outputs are clamped to the respective external voltage applied at aclamp_ when an alarm condition is triggered. if an alarm condition is triggered, the alm_clmp bits are overwritten to 00, causing a permanent clamp condition. clear this permanent clamp condition with a subsequent write to reset the alm_clmp bits. table 12c. alarm clamp modes vghyst1 vghyst0 function 0 0 8 lsbs of hysteresis. 0 1 16 lsbs of hysteresis. 1 0 32 lsbs of hysteresis. 1 1 64 lsbs of hysteresis. table 12a. gate voltage hysteresis levels
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 42 ______________________________________________________________________________________ bit name data bit reset state function x d15?12 x don? care. valarm2 d11 0 channel 2 gate voltage alarm bit. set to 1 to enable the alarm functionality for gate2 voltage measurements. set to 0 to disable the alarm functionality for gate2 voltage measurements. vwin2 d10 0 channel 2 gate voltage windowing bit. set to 1 to monitor the gate2 voltage with the alarm comparator in windowing mode. set to 0 to monitor the gate2 voltage with the alarm comparator in hysteresis mode. talarm2 d9 0 channel 2 temperature alarm bit. set to 1 to enable the alarm functionality for channel 2 temperature measurements. set to 0 to disable the alarm functionality for channel 2 temperature measurements. twin2 d8 0 channel 2 temperature windowing bit. set to 1 to monitor the channel 2 temperature with the alarm comparator in windowing mode. set to 0 to monitor the channel 2 temperature with the alarm comparator in hysteresis mode. ialarm2 d7 0 channel 2 sense voltage alarm bit. set to 1 to enable the alarm functionality for channel 2 sense voltage measurements. set to 0 to disable the alarm functionality for channel 2 sense voltage measurements. iwin2 d6 0 channel 2 sense voltage windowing bit. set to 1 to monitor the channel 2 sense voltage with the alarm comparator in windowing mode. set to 0 to monitor the channel 2 sense voltage with the alarm comparator in hysteresis mode. valarm1 d5 0 channel 1 gate voltage alarm bit. set to 1 to enable the alarm functionality for gate1 voltage measurements. set to 0 to disable the alarm functionality for gate1 voltage measurements. vwin1 d4 0 channel 1 gate voltage windowing bit. set to 1 to monitor the gate1 voltage with the alarm comparator in windowing mode. set to 0 to monitor the gate1 voltage with the alarm comparator in hysteresis mode. talarm1 d3 0 channel 1 temperature alarm bit. set to 1 to enable the alarm functionality for channel 1 temperature measurements. set to 0 to disable the alarm functionality for channel 1 temperature measurements. twin1 d2 0 channel 1 temperature windowing bit. set to 1 to monitor the channel 1 temperature with the alarm comparator in windowing mode. set to 0 to monitor the channel 1 temperature with the alarm comparator in hysteresis mode. ialarm1 d1 0 channel 1 sense voltage alarm bit. set to 1 to enable the alarm functionality for channel 1 sense voltage measurements. set to 0 to disable the alarm functionality for channel 1 sense voltage measurements. iwin1 d0 0 channel 1 sense voltage windowing bit. set to 1 to monitor the channel 1 sense voltage with the alarm comparator in windowing mode. set to 0 to monitor the channel 1 sense voltage with the alarm comparator in hysteresis mode. table 13. almscfg (read/write)
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 43 set the valarm1 bit, d5, to 1 to enable alarm function- ality for gate1 voltage measurements. set the vwin1 bit, d4, to 1 to monitor the gate1 voltage with the alarm comparator in windowing mode. set vwin1 to 0 to monitor the gate1 voltage with the alarm compara- tor in hysteresis mode. set the talarm1 bit, d3, to 1 to enable alarm functionality for channel 1 temperature measurements. set the twin1 bit, d2, to 1 to monitor the channel 1 temperature with the alarm comparator in windowing mode. set twin1 to 0 to monitor the channel 1 temperature with the alarm comparator in hysteresis mode. set the ialarm1 bit, d1, to 1 to enable alarm functionality for channel 1 sense voltage (rcs1+ to rcs1-) measurements. set the iwin1 bit, d0, to 1 to monitor the channel 1 sense voltage with the alarm comparator in windowing mode. set iwin1 to 0 to moni- tor the channel 1 sense voltage with the alarm com- parator in hysteresis mode. vset1 and vset2 (write) write to the channel 1/channel 2 v set registers to set the v set(code) code in the v dac(code) equations. writing to these registers triggers a v dac(code) calcu- lation. that code is then loaded into either the channel 1/channel 2 dac input register or channel 1/channel 2 dac input and output register, depending on the state of the ldac1/ldac2 bits in the software configuration register. set the command byte to 40h to write to the channel 1 v set register. set the command byte to 42h to write to the channel 2 v set register. see table 14. bits d15?12 are don? care. bits d11?0 contain the straight binary data. usrk1 and usrk2 (write) write to the channel 1/channel 2 k parameter registers to set the lut k [k] code in the v dac(code) equation. the k parameter register value is loaded into the v dac(code) equation when the ksrc_ bits in the soft- ware configuration register are set to 010, 101, 110, or 111. see table 11b. use the k parameter as an index to the k lut or as a multiplier for the v dac(code) equation in place of v set(code) by writing to the soft- ware configuration register. see table 11. set the com- mand byte to 44h to write to the channel 1 k parameter register. set the command byte to 46h to write to the channel 2 k parameter register. see table 15. bits d15?12 are don? care. bits d11?0 contain the straight binary data. ipdac1 and ipdac2 (write) write to the channel 1/channel 2 dac input registers to load the dac code and bypass a v dac(code) calcula- tion. transfer the code written to the dac input registers to the channel 1/channel 2 dac output registers by set- ting the corresponding dacch_ bit high in the software load dac register. set the command byte to 48h and 4ch, respectively, to write to the channel 1/channel 2 dac input registers. see table 16. bits d15?12 are don? care. bits d11?0 contain the straight binary data. writing to these registers overwrites any previous val- ues loaded from the v dac(code) calculation. table 14. vset1 and vset2 (write) bit name data bit reset state function x d15?12 x don? care. vset11?set0 d11?0 0000 0000 0000 vset11 is the msb and vset0 is the lsb. data format is straight binary. table 15. usrk1 and usrk2 (write) bit name data bit reset state function x d15?12 x don? care. k11?0 d11?0 n/a k11 is the msb and k0 is the lsb. data format is straight binary.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 44 ______________________________________________________________________________________ thrudac1 and thrudac2 (write) write to the channel 1/channel 2 dac input and output registers to load the dac code directly to the respec- tive dac output and bypass a v dac(code) calculation. set the command byte to 4ah and 4eh, respectively, to write to the channel 1/channel 2 dac input and output registers. see table 17. bits d15?12 are don? care. bits d11?0 contain the straight binary data. writing to these registers overwrites any previous val- ues loaded from the v dac(code) calculation. pgacal (write) write to the pga calibration control register to calibrate the channel 1 and channel 2 current-sense amplifiers. set the command byte to 5eh to write to the pga cali- bration control register. see table 18. bits d15?5 are don? care. set the hvcal2 bit, d4, to 1 to short circuit the channel 2 current-sense amplifier inputs so that only the offset is apparent at the pgaout2 output. set the hvcal1 bit, d3, to 1 short circuit the channel 1 cur- rent-sense amplifier inputs so that only the offset is apparent at the pgaout1 output. determine the input channel offset (+12mv, typ) by setting the hvcal_bits and commanding a sense-voltage adc conversion. table 16. ipdac1 and ipdac2 (write) bit name data bit reset state function x d15?12 x don? care. dac11?ac0 d11?0 0000 0000 0000 dac11 is the msb and dac0 is the lsb. data format is straight binary. table 17. thrudac1 and thrudac2 (write) bit name data bit reset state function x d15?12 x don? care. dac11?ac0 d11?0 n/a dac11 is the msb and dac0 is the lsb. data format is straight binary. table 18. pgacal (write) bit name data bit reset state function x d15?5 x don? care. hvcal2 d4 0 channel 2 high-side calibration bit. set to 1 to short circuit the current- sense amplifier inputs so that only the offset is apparent at the pgaout2 output and the channel 2 current-sense conversion. hvcal1 d3 0 channel 1 high-side calibration bit. set to 1 to short circuit the current- sense amplifier inputs so that only the offset is apparent at the pgaout1 output and the channel 1 current-sense conversion. track d2 0 acquisition/tracking bit. set to 0 to force the next current-sense calibration to run in acquisition mode. set to 1 to force the next calibration to run in tracking mode. set track to 0 the first time through a calibration. docal d1 0 dual calibration bit. set to 1 to run a current-sense self-calibration routine in both channels 1 and 2. at the end of the calibration routine, docal is set to 0. when docal and selftime are both set to 1, the internal timer is reset at the end of the routine and waits another 13ms before performing the next self-timed calibration. selftime d0 0 self-time bit. set to 1 to perform a calibration of the current-sense amplifier in both channels 1 and 2 on a self-timed periodic basis (approximately every 15ms). when set to the default state of 0, calibration only occurs when docal is set to 1.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 45 the current-sense calibration routine offers two opera- tion modes: acquisition and tracking. in acquisition mode, the calibration routine operates continuously until the error is minimized to 50? or less. in tracking mode, the routine operates every 15ms to minimize interference and allow the calibration routine more averaging time. a sample-and-hold circuit prevents switching noise on gate_ during tracking mode. set the track bit, d2, to 0 to run the calibration routine in acquisition mode. set track to 1 to run the calibration routine in tracking mode. set track to 0 for the first calibration. set the docal bit, d1, to 1 to run a current-sense self-calibration routine in both channel 1 and channel 2. at the end of the calibration routine, docal is set back to 0. set the selftime bit, d0, to 1 to perform a cur- rent-sense calibration on a periodic basis, typically every 15ms. use the docal bit in conjunction with the selftime bit. when a calibration routine is command- ed by docal, and selftime is set to 1, the internal timer is reset at the end of the routine and waits another 15ms before performing the next self-timed calibration. the self-calibration routine can be commanded when the dacs are powered down, but the results are not accurate. for best results, run the calibration after the dac power-up time, t dpuext . adccon (write) write to the adc conversion register to convert the adcin_, gate_, internal dac and sense voltages. the adc conversion register also converts the internal and external temperature readings and sets the interface for continuous conversion. see table 19. set the com- mand byte to 62h to write to the adc conversion regis- ter. bits d15?12 are don?-care bits. the adcmon bit in the hardware configuration register must be set to 1 to load adc results into the fifo. set the conconv bit, d11, to 1 for continuous adc conversions. set the ch10 bit, d10, to 1 to convert the adcin2 volt- age. set the ch9 bit, d9, to 1 to convert the gate2 voltage. set the ch8 bit, d8, to 1 to convert the channel 2 dac code. set the ch7 bit, d7, to 1 to convert the channel 2 sense voltage. set the ch6 bit, d6, to 1 to convert the channel 2 external temperature sensor measurement. set the ch5 bit, d5, to 1 to convert the adcin1 voltage. set the ch4 bit, d4, to 1 to convert the gate1 voltage. set the ch3 bit, d3, to 1 to convert the channel 1 dac code. set the ch2 bit, d2, to 1 to convert the channel 1 sense voltage. set the ch1 bit, d1, to 1 to convert the channel 1 external temperature sensor measurement. set the ch0 bit, d0, to 1 to con- vert the internal temperature sensor measurement. convert any combination of adc channels through the adc conversion register. when requesting a conver- sion of more than one channel, the channels are con- verted in numerical order from ch0 to ch10. setting the conconv bit to 1 may cause the fifo to overflow if data is not read out quickly enough. continuous-conversion mode is only available in clock modes 00 and 01. see the clock mode 00 and clock mode 01 sections. the adc does not trigger a busy signal when the conconv bit is set. if a temperature channel is included in the scan when conconv is set, the internal reference and temperature sensor remain powered up until conconv is set to 0. similarly, if an adc measurement using the internal reference is included in the scan, the internal reference is turned on prior to the first conversion and remains on until conconv is set to 0. in clock modes 00 and 01, when the conconv bit is set to 0 and the current scan (not just the current con- version) is completed, the adc goes to an idle state awaiting the next command. the busy output is set high when the conconv bit is set to 0 and remains high until the current scan is completed. see the busy output section . shut (write) shut down all internal blocks, as well as the dacs, adcs, and gate-drive amplifiers individually, through the shutdown register. see table 20. set the command byte to 64h to write to the shutdown register. bits d15?12 are don? care. set the fullpd bit, d11, to 1 to shut down all internal blocks and reduce av dd sup- ply current to 0.8?. the fullpd bit is set to 1 at power-up. set the fullpd bit to 0 before writing any other commands to activate all internal blocks and functionality. set the fbgon bit, d10, to 1 to keep the internal bandgap reference powered up. set the wdgpd bit, d9, to 1 to turn off the watchdog oscillator and prevent self-monitoring of the watchdog timer. set the oscpd bit, d8, to 1 to power down the internal oscillator. set the pd2-3 bit, d7, to 1 to power down the channel 2 current-sense amplifier. set the pd2-2 bit, d6, to 1 to power down the channel 2 gate-drive amplifier. set the pd2-1 bit, d5, to 1 to power down the channel 2 dac summing node. set the pd2-0 bit, d4, to 1 to power down the channel 2 dac. set the pd1-3 bit, d3, to 1 to power down the channel 1 current-sense amplifier. set the pd1-2 bit, d2, to 1 to power down the channel 1 gate-drive amplifier. set the pd1-1 bit, d1, to 1 to power down the channel 1 dac summing node. set the pd1-0 bit, d0, to 1 to power down the channel 1 dac.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 46 ______________________________________________________________________________________ for maximum accuracy, power up all internal blocks prior to a calibration (max11014). the max11015 does not require the current-sense amplifier to be powered up for a calibration. ldac (write) write to the software load dac register to load the val- ues stored in the dac input registers to their respective dac output registers. set the command byte to 66h to write to the software load dac register. see table 21. bits d15?2 are don? care. set the dacch2 bit, d1, to 1 to load the channel 2 dac output register with the value stored in the chan- nel 2 dac input register. set the dacch1 bit, d0, to 1 to load the channel 1 dac output register with the value stored in the channel 1 dac input register. see figure 20. table 19. adccon (write) bit name data bit reset state function x d15?12 x don? care. conconv d11 0 set to 1 to command continuous adc conversions. the adcmon bit in the hardware configuration register must be to set to 1 to load adc results into the fifo. continuous conversions are only applicable in clock modes 00 and 01. when conconv is set to 1, the adc continuously converts the channels selected by the adc conversion register using the conversion mode selected by the cksel1/cksel0 bits. results are accumulated in the fifo. empty the fifo quickly enough to prevent overflow conditions. ch10 d10 0 set to 1 to convert the adcin2 voltage in the next adc conversion cycle. ch9 d9 0 set to 1 to convert the gate2 voltage in the next adc conversion cycle. also, the pd2-3 bit in the shutdown register must be set to 0. ch8 d8 0 set to 1 to convert the channel 2 dac code in the next adc conversion cycle. ch7 d7 0 set to 1 to convert the channel 2 sense voltage in the next adc conversion cycle. ch6 d6 0 set to 1 to convert the channel 2 external temperature-sensor measurement in the next adc conversion cycle. ch5 d5 0 set to 1 to convert the adcin1 voltage in the next adc conversion cycle. ch4 d4 0 set to 1 to convert the gate1 voltage in the next adc conversion cycle. also, the pd1-3 bit in the shutdown register must be set to 0. ch3 d3 0 set to 1 to convert the channel 1 dac code in the next adc conversion cycle. ch2 d2 0 set to 1 to convert the channel 1 sense voltage in the next adc conversion cycle. ch1 d1 0 set to 1 to convert the channel 1 external temperature sensor measurement in the next adc conversion cycle. ch0 d0 0 set to 1 to convert the internal temperature sensor measurement in the next adc conversion cycle.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 47 table 20. shut (write) table 21. ldac (write) bit name data bit reset state function x d15?12 x don? care. fullpd d11 1 set to 1 to power down all internal blocks. fullpd takes precedence over any of the other power-down control bits. all commands in progress are suspended and the dacs and adc are disabled. the serial interface remains functional. fullpd is set to 1 on power-up. set the fullpd bit to 0 after power-up and before writing any other commands to activate all internal blocks. fbgon d10 0 set to 1 to force the internal bandgap voltage block to power up, remain powered up between conversions, and avoid the 50? reference power- up delay time. forcing the internal reference to remain on increases the power dissipation. set fbgon to its default state of 0 to power the bandgap voltage as required by the adc. wdgpd d9 0 set to 1 to turn off the watchdog oscillator. the watchdog oscillator monitors the internal alu and resets the logic state to the startup condition after 80ms. this reduces power consumption but prevents the self-monitoring function of the watchdog timer. oscpd d8 0 set to 1 to power down the internal oscillator. oscpd is automatically reset to 0 after receiving the next interface command. pd2-3 d7 1 set to 1 to power down the channel 2 current-sense amplifier. pd2-2 d6 1 set to 1 to power down the channel 2 gate-drive amplifier. pd2-1 d5 1 set to 1 to power down the channel 2 dac summing node (max11014)/dac buffer (max11015). the summing node acts as a buffer in the max11015. pd2-0 d4 1 set to 1 to power down the channel 2 dac. pd1-3 d3 1 set to 1 to power down the channel 1 current-sense amplifier. pd1-2 d2 1 set to 1 to power down the channel 1 gate-drive amplifier. pd1-1 d1 1 set to 1 to power down the channel 1 dac summing node (max11014)/dac buffer (max11015). the summing node acts as a buffer in the max11015. pd1-0 d0 1 set to 1 to power down the channel 1 dac. bit name data bit reset state function x d15?2 x don? care. dacch2 d1 n/a set to 1 to load the channel 2 dac output register with the value stored in the channel 2 dac input register. dacch1 d0 n/a set to 1 to load the channel 1 dac output register with the value stored in the channel 1 dac input register.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 48 ______________________________________________________________________________________ sclr (write) write to the software clear register to reset all of the internal registers, clear the internal alu or reset the fifo pointers and clear the fifo. this register also resets the alarm threshold registers, alarm flag reg- ister and the dac registers. set the command byte to 74h to write to the software clear register. see table 22. bits d15?7 are don? care. the fullreset bit, d6, and armreset bit, d5, provide functionality for a full reset. write the following sequence to perform a full reset and return all internal register bits to their respec- tive reset state: write to the software clear register once with fullreset = 0 and armreset = 1. write a second word to the software clear register with fullreset = 1 and armreset = 0. the full reset takes effect after completion of the second write to this register. set the almsclr bit, d4, to 1 to reset all alarm thresh- old register bits and the alarm flag register bits. set the cacheclr bit, d3, to 1 to force the alu to clear the pointers and lookup value cache to their power-up val- ues. this forces a lut operation and a v dac(code) cal- culation for the next sample, regardless of whether the sample produces a table pointer that is different. set the fifoclr bit, d2, to 1, reset the fifo address pointers, and clear the fifo? contents. set the dac2clr bit, d1, to 1 to reset the channel 2 dac input and output register bits. set the dac1clr bit, d0, to 1 to reset the channel 1 dac input and output register bits. table 22. sclr (write) table 23. lutadd (write) bit name data bit reset state function x d15?7 x don? care. fullreset d6 n/a armreset d5 0 write the following sequence to perform a full reset and return all internal registers to their respective reset state: write to the software clear register once with fullreset = 0 and armreset = 1. write a second word to the software clear register with fullreset = 1 and armreset = 0. the full reset takes effect after completion of the second write to this register. after a full software reset, the internal registers return to their power-on state, but the internal oscillator remains running (unlike at power-up). after a full software reset, it is not necessary to set the fullpd bit to 0 (as it is on a normal power-on reset) before attempting any other commands. the busy output is set high and the alu initializes internal ram before setting busy low. almsclr d4 n/a set to 1 to reset all alarm threshold registers and the alarm flag register. cacheclr d3 n/a set to 1 to force the alu to clear the pointers and lookup value cache to their power-up values. this forces an lut operation and a v dac(code) calculation for the next sample, regardless of whether the sample produces a table pointer that is different. fifoclr d2 n/a set to 1 to reset the fifo address pointers and clear the fifo? contents. dac2clr d1 n/a set to 1 to reset the channel 2 dac input and output registers. dac1clr d0 n/a set to 1 to reset the channel 1 dac input and output registers. bit name data bit reset state function lutword7 lutword0 d15?8 0000 0000 set these 8 bits to determine the number of lut words to be read/written. lutadd7 lutadd0 d7?0 0000 0000 set these 8 bits to determine the base address for the read/write operation.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 49 lutadd (write) write to the lut address register to determine the num- ber of write/read lut locations, the base address pointer, and the lut configuration word. see table 23. set the command byte to 7ah to write to the lut address register. set the lutword bits, d15?8, to the number of lut words to be read/written. set the lutadd bits, d7?0, to determine the base address for the read/write operation. if the top of lut memory is reached before the lutword limit is reached, the lut data register read/write is discontinued. write 00h to the lutword bits to abort an lut read/write. see the sram lut s section for details on programming the various lut addresses. see table 28 for a map of the lut address locations. lutdat (read/write) write or read lut data through the lut data register. set the command byte to 7ch to write to the lut data register. set the command byte to fch to read from the lut data register. write 16 bits of data to the lut data register to load individual address locations with lookup data. see table 24. the address in the lut memory space is automatically incremented after each lut data register write command. differentiate lut data from adc data from the unique lut data channel tag 110_. see table 25. table 24. lutdat (read/write) bit name data bit reset state function lutdat15 lutdat0 d15?0 n/a the 16-bit data word written to the lut data or configuration memory space. table 25. fifo data bits channel tag d15 d14 d13 d12 d11 d10?1 d0 conversion-data origin 0000 msb lsb internal temperature sensor. 0001 msb lsb channel 1 external temperature sensor. 0010 msb lsb channel 1 sense voltage. 0011 msb lsb channel 1 dac input register. 0100 msb lsb channel 1 gate voltage. 0101 msb lsb adcin1 voltage. 0110 msb lsb channel 2 external temperature sensor. 0111 msb lsb channel 2 sense voltage. 1000 msb lsb channel 2 dac input register. 1001 msb lsb channel 2 gate voltage. 1010 msb lsb adcin2 voltage. 1011 msb lsb reserved. 1 1 0 d12 d11 lsb lut data value. see table 28. bit d12 is the msb for the lut configuration words. bit d11 is the msb for all other lut reads. 1110 msb lsb conversion may be corrupted. this occurs only when arriving data causes the fifo to overflow at the same time data is being read out. 1111 msb lsb empty fifo. the current value of the flag register is read out in place of the fifo data.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 50 ______________________________________________________________________________________ fifo read the oldest result in the fifo by writing command byte 80h and reading the next 16 bits at dout in spi mode and sda in i 2 c mode. bits d15?12 (channel tag) identify which adc or lut channel is being con- verted. bits d11?0 contain the adc/lut conversion results for that specific channel. bit d11 is the msb and bit d0 is the lsb for all adc and lut data, with the exception of the lut configuration words. when read- ing the lut configuration registers, bit d12 is the msb and bit d0 is the lsb. see table 25. flag (read) read from the flag register to determine the source of a busy condition. set the command byte to f6h to read the flag register. bits d15?7 are don? care. see table 26. the restart bit, d6, is set to 1 after either a watchdog timer reset or by commanding a software reset through the software clear register? full reset function. restart is reset to a 0 after a power-on reset or a flag register read command. the alubusy bit, d5, is set to 1 when the alu is performing other tasks not covered by specific status bits elsewhere in this register. the pgabusy bit, d4, is set to 1 when the alu is performing a pga calibration. table 26. flag (read) bit name data bit reset function x d15?7 x don? care. restart d6 0 restart is set to 1 after either a watchdog timer reset or by commanding a software reset through the software clear register? full reset function. restart returns to 0 after a power-on reset or a flag register read command. alubusy d5 0 alubusy is set to 1 when the alu is performing other tasks not covered by specific status bits elsewhere in this register. this includes, for example, the internal memory initialization after power-up. pgabusy d4 0 pgabusy is set to 1 when the alu is performing a pga calibration (whether commanded or self-timed). adcbusy d3 0 adcbusy is set to 1 when the adc is busy, an alarm value is being checked, or the adc results are being loaded into the fifo. adcbusy returns to 0 after the adc completes all of the conversions in the current scan. vgbusy d2 1 vgbusy is set to 1 when the alu is performing a lookup and interpolation or v dac(code) calculation for either channel. fifoemp d1 1 fifoemp is set to 1 when the fifo is empty and contains no data. fifoemp is reset to 0 if data is written into the fifo. writing to the software clear register with fifoclr set to 1 causes the fifo to be cleared, which then sets fifoemp to 1. fifoovr d0 0 fifoovr functions in one of two modes: 1) reading the adc data: fifoovr is set to 1 if the fifo has a data overflow. fifoovr is reset to 0 by reading the flag register or by clearing the fifo through the software clear register. emptying the fifo does not clear the fifoovr bit. 2) reading the lut data: when commanding an lut read, the fifo is no longer allowed to overflow (as it is for normal adc monitoring). fifoovr is set to 1 if the lut is full and set to 0 if the lut is not full, for that instant in time only.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 51 table 27. almflag (read) bit name data bit reset state function x d15?12 x don? care. high-v2 d11 0 high-v2 is set to 1 when the gate2 voltage exceeds the high threshold setting. high-v2 is reset to 0 by either a read of the alarm flag register or a software clear command. low-v2 d10 0 low-v2 is set to 1 when the gate2 voltage decreases below the low threshold setting. low-v2 is reset to 0 by either a read of the alarm flag register or a software clear command. high-i2 d9 0 high-i2 is set to 1 when the channel 2 sense voltage exceeds the high threshold setting. high-i2 is reset to 0 by either a read of the alarm flag register or a software clear command. low-i2 d8 0 low-i2 is set to 1 when the channel 2 sense voltage decreases below the low threshold setting. low-i2 is reset to 0 by either a read of the alarm flag register or a software clear command. high-t2 d7 0 high-t2 is set to 1 when the channel 2 external temperature exceeds the high threshold setting. high-t2 is reset to 0 by either a read of the alarm flag register or a software clear command. low-t2 d6 0 low-t2 is set to a 1 when the channel 2 external temperature decreases below the low threshold setting. low-t2 is reset to 0 by either a read of the alarm flag register or a software clear command. high-v1 d5 0 high-v1 is set to 1 when the gate1 voltage exceeds the high threshold setting. high-v1 is reset to 0 by either a read of the alarm flag register or a software clear command. low-v1 d4 0 low-v1 is set to 1 when the gate1 voltage decreases below the low threshold setting. low-v1 is reset to 0 by either a read of the alarm flag register or a software clear command. high-i1 d3 0 high-i1 is set to 1 when the channel 1 sense voltage exceeds the high threshold setting. high-i1 is reset to 0 by either a read of the alarm flag register or a software clear command. low-i1 d2 0 low-i1 is set to 1 when the channel 1 sense voltage decreases below the low threshold setting. low-i1 is reset to 0 by either a read of the alarm flag register or a software clear command. high-t1 d1 0 high-t1 is set to 1 when the channel 1 external temperature exceeds the high threshold setting. high-t1 is reset to 0 by either a read of the alarm flag register or a software clear command. low-t1 d0 0 low-t1 is set to a 1 when the channel 1 external temperature decreases below the low threshold setting. low-t1 is reset to 0 by either a read of the alarm flag register or a software clear command.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 52 ______________________________________________________________________________________ the adcbusy bit, d3, is set to 1 when the adc is busy, an alarm value is being checked, or the adc results are being loaded into the fifo. adcbusy returns to 0 after the adc completes all of the conver- sions in the current scan. the vgbusy bit, d2, is set to 1 when the alu is performing a lookup and interpola- tion or v dac(code) calculation for either channel. the fifoemp bit, d1, is set to 1 when the fifo is empty and contains no data. fifoemp is reset to 0 if data is written into the fifo. writing to the software clear regis- ter with fifoclr set to 1 causes the fifo to be cleared, which then sets fifoemp to 1. the functionality of the fifoovr bit, d0, depends on whether the fifo is loaded with adc data or lut data. fifoovr functions in one of two modes: 1) reading the adc data: fifoovr is set to 1 if the fifo has a data overflow. fifoovr is reset to 0 only by reading the flag register or by clearing the fifo through the software clear register. emptying the fifo does not clear the fifoovr bit. 2) reading the lut data: when commanding a lut read, the fifo is no longer allowed to overflow. fifoovr is set to 1 if the lut is full and set to 0 if the lut is not full, for that instant in time only. see the fifo description section. almflag (read) read the alarm flag register to determine the source of an alarm condition. set the command byte to f8h to read the alarm flag register. bits d15?12 are don? care. see table 27. bits d11?0 are all reset to 0 following a read of the alarm flag register or a software clear com- mand. the high-v2 bit, d11, is set to 1 when the gate2 voltage exceeds the high threshold setting. the low-v2 bit, d10, is set to 1 when the gate2 voltage decreases below the low threshold setting. the high-i2 bit, d9, is set to 1 when the channel 2 sense voltage exceeds the high threshold setting. the low-i2 bit, d8, is set to 1 when the channel 2 sense voltage decreases below the low threshold setting. the high-t2 bit, d7, is set to 1 when the channel 2 external temperature exceeds the high threshold setting. the low-t2 bit, d6, is set to a 1 when the channel 2 external temperature decreases below the low threshold setting. the high-v1 bit, d5, is set to 1 when the gate1 volt- age exceeds the high threshold setting. the low-v1 bit, d4, is set to 1 when the gate1 voltage decreases below the low threshold setting. the high-i1 bit, d3, is set to 1 when the channel 1 sense voltage exceeds the high threshold setting. the low-i1 bit, d2, is set to 1 when the channel 1 sense voltage decreases below the low threshold setting. the high-t1 bit, d1, is set to 1 when the channel 1 external temperature exceeds the high threshold setting. the low-t1 bit, d0, is set to a 1 when the channel 1 external temperature decreases below the low threshold setting. fifo description the max11014/max11015? fifo stores 15 adc sam- ples or 16 sram lut data words. read the fifo to load the fifo data onto dout in spi mode and sda in i 2 c mode. see table 25. the adc sample data includes a 4-bit channel tag, followed by 12 bits of data. the adc channel tags indicate the source for the temperature or voltage result. the lut data includes a 3-bit channel tag for lut configuration word data and a 4-bit tag for all other lut data. the lut tags indicate whether the lut data is temperature (t) or numerical (k)-based. do not mix adc results with lut results in the fifo. the fifo allows overflows of adc data and it always contains the 15 most recent adc conversion results. read the fifo quickly enough to prevent an overflow condition. detect if the fifo has overflowed (indicating a loss of data) by inspecting the fifoovr bit in the flag register. the fifo does not overflow while outputting sram lut data. count how many words are output in order (through the numerical representation of the lutword bits in the lut address register) to tell which lut data word is being supplied. adc monitoring mode each time the adc converts a sample in adc monitor- ing mode, the data word and its 4-bit channel tag are moved into the fifo. load the data from the fifo to dout in spi mode and sda in i 2 c mode by writing command byte 80h. the hardware configuration register? adcmon bit determines whether adc samples are loaded into the fifo. see table 10. set adcmon to 1 to store adc samples in the fifo. set to 0 to not load adc results into the fifo. the value of adcmon does not affect whether the results from any particular adc conversion are checked against the alarm thresholds or exam- ined for changes to the v dac(code) equations. after reading out all of the adc fifo data, the flag regis- ter sets the fifoemp bit to 1. if a fifo read command is issued with the fifo empty, the fifo returns a channel tag of 1111 and the 12 flag register bits. see table 25. the fifo allows interface reads to be simultaneous with the arrival of new adc sample or lut data words. but when the fifo is full and overflowing, if an adc sample arrives at exactly the same time as an interface read, there is a possibility of data corruption. this condition is
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 53 indicated by channel tag 1110 (rather than the usual adc channel tag). in this case, only that particular data item is corrupted and all other fifo contents remain valid and can be accessed with subsequent reads. read the fifo quickly enough to prevent overflow conditions to entirely avoid the risk of data corruption. at fast serial-interface clock rates, it is possible to read data from the fifo faster than the adc loads it. set a continu- ous adc scan in progress and continuously read the fifo. assuming the fifo is being emptied more quickly than it is being filled, the continuous fifo reads supply a mixture of empty channel tags (1111 and the flag regis- ter value), mixed in with the valid adc results. separate the valid adc results from the flag register data based on the 4-bit channel tag. sram lut read mode after an lut data register read command, data from the sram luts is copied into the fifo. load the data from the fifo to dout in spi mode and sda in i 2 c mode by reading the fifo. if sram lut data is written to the fifo faster than its read out, the fifo fills up. the copying of data is suspended until the fifo is read again. if the fifo is read more quickly than the sram lut loads the values, the data is interspersed with error channel tags (1111 and the flag register value) and valid lut data. output data format all conversion data results are output in 2-byte format, msb first. data transitions on dout on the falling edges of sclk in spi mode. data transitions on sda on the rising edge of scl in i 2 c mode. figures 10, 18, and 19 illustrate the max11014/max11015? read tim- ing. see figures 21 and 22 for adc and temperature transfer functions, respectively. adc transfer function data is output in straight binary format, with the excep- tion of temperature results/alarms, which are two? complement. figure 21 shows the unipolar transfer function for single-ended inputs. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = v refadc / 2.5v for unipolar operation, and 1 lsb = +0.125? for tem- perature measurements. pgaout outputs the pgaout output voltages are derived from a sense voltage conversion. the dual current-sense amplifiers amplify the voltage between rcs_+ and rcs_- by four and add an offset voltage (+12mv nominally). the cur- rent-sense amplifiers scale voltages up to +625mv. the max11014? class a control loop detailed in figure 5. the max11015? class ab analog control is detailed in figure 6. calculate the pgaout_ voltage with the fol- lowing equation: vv xvv mv pgaout refadc rcs rcs =? +??+ [ ( ) ] 412 full-scale transition input voltage (lsb) offset binary output code (lsb) fs - 3/2 lsb 0 000...000 000...001 000...010 000...011 111...111 111...110 111...101 fs = v refadc 1 lsb = v refadc / 4096 fs 123 output code 011....111 temperature c 011....110 000....001 111....101 100....001 100....000 111....111 111....110 000....000 0 000....010 -256 c +255.5 c figure 21. adc transfer function figure 22. temperature transfer function
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 54 ______________________________________________________________________________________ write to the hvcal_ bits in the pga calibration control register to short circuit the current-sense amplifier inputs so that only the offset is apparent at the pgaout_ output and adc input. busy output the busy output goes high for a variety of reasons. the possible causes of busy pulsing high include: the adc is converting, but not in continuous con- version mode the internal alu core is performing a power-up initialization the internal alu core is performing a v dac(code) calculation the internal alu core is performing another function the self-calibration routine is taking place when the conconv bit is set in the adc conversion register, the busy output does not trigger when the adc is converting (for all clock modes). this prevents the continuous adc activity from masking other busy events. the serial interface remains available regardless of the state of busy, although certain commands are not appropriate. for example, if busy is high for an adc operation, reading the fifo does not produce the result for the current conversion. also, if busy triggers due to an adc conversion, do not enter a second con- version command until busy returns low, indicating the previous conversion is complete. see figure 23 for a pair of busy timing examples. in example 1, an externally timed adc conversion trig- gers the adcbusy bit in the flag register and forces busy high. next, a v dac(code) calculation triggers the alubusy bit in the flag register and holds busy high. in example 2, the v dac(code) calculation is not requested. cnvst gate1/2 output busy (output) busy timing: example 1 adcbusy (flag register bit) alubusy (flag register bit) cnvst busy output adcbusy (flag register bit) alubusy (flag register bit) busy timing: example 2 figure 23. busy timing
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 55 figure 24. alarm window comparator example window of values that do n0t trigger an alarm 1111 1111 1111 most positive value (default for high threshold registers) 0000 0000 0000 most negative value (default for low threshold registers) high threshold register value low threshold register value actual measurement value; therefore, alarm triggers built in 8?4 lsbs of hysteresis built in 8?4 lsbs of hysteresis high threshold register voltage or temperature measurement value alarm comparator (active-low) time alarm interrupt (active-low) read alarm flag register read alarm flag register read alarm flag register built-in hysteresis low threshold register built-in hysteresis figure 25. alarm window-mode timing example
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 56 ______________________________________________________________________________________ alarm output the alarm output asserts when the corresponding channel? temperature or voltage readings exceed the respective high or low alarm threshold. each time the sense voltage, temperature (external for either channel, internal for channel 2), or gate_ voltage is converted, the measured value is compared to the high and low alarm threshold values. the alarm comparison operates in either window or hysteresis mode. when operating in window compara- tor mode (twin_, iwin_, or vgwin_ bits in the soft- ware alarm configuration register set to 1), the adc output values are monitored to ensure that the values are between both the high and low alarm threshold register values. see table 13 and figure 24. window comparisons include built-in hysteresis levels, ensuring the alarm output does not trigger repeatedly when sampling values around the threshold. the almhyst bits in the hardware alarm configuration register vary the built-in hysteresis between 8 and 64 lsbs. the built-in hysteresis acts as a noise filter to prevent unnecessary switching when a sample value is varying slightly around the threshold. the alarm condi- tion remains in place until the measured value rises above the low threshold value or falls below the high threshold value. figure 25 details a window-mode tim- ing example. the alarm output operates in interrupt or comparator mode. in interrupt mode, the alarm output asserts until the alarm flag register is read. in comparator mode, the alarm output reflects the internal alarm state and remains asserted for as long as the alarm conditions are breached. the alarm output deasserts after the win- dowing or hysteresis conditions are satisfied. when operating in hysteresis comparator mode (twin_, iwin_, or vgwin_ bits in the software alarm configuration register set to 0), the adc output values are monitored to ensure that the values are below the figure 26. alarm hysteresis comparator example window of values that do not trigger an alarm 1111 1111 1111 most positive value (default for high threshold registers) 0000 0000 0000 most negative value (default for low threshold registers) high threshold register value low threshold register value actual measurement value, therefore alarm triggers alarm removed after crossing back below this level alarm triggered when exceeding this level
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 57 high set alarm threshold register value. see figure 26. if an adc output value exceeds its respective alarm high threshold register value, the alarm out- put triggers. the alarm condition remains in place until the measured value falls below the low threshold value. figure 27 details a hysteresis-mode timing example. when operating in interrupt mode, the alarm output triggers when the measured adc output value exceeds either the high or low threshold. however, in interrupt mode, the alarm output remains active until reading the alarm flag register. reading the alarm flag reg- ister resets the flag bits and the alarm output. the default values for the high and low threshold regis- ters are the extremes of the measured range (all 1s or all 0s, respectively). the alarm output can be config- ured to be open-drain or push-pull and active-high or active-low through the hardware alarm configuration register. see table 12. at power-up, the alarm output is configured as an active-high output that operates in interrupt mode. automatic gate clamping configure the alarm output to clamp the gate1 out- put to aclamp1 or gate2 output to aclamp2 in response to an alarm condition through the hardware alarm configuration register. see table 12c. set the alm_clmp_ bits, d5?2, to clamp the respective channel? gate output. each channel has four possible alm_clmp1/ alm_clmp0 values: alm_clmp1/alm_clmp0 = 00 power-on reset state. gate_ clamps through a series 2.4k resistor to the aclamp_, regardless of any alarm condition. reset these 2 bits before attempting to change the dac voltage. alm_clmp1/alm_clmp0 = 01 the automatic gate_ clamp is disabled in this mode. the gate_ outputs are not affected by any alarm conditions. the alarm output function operates nor- mally (samples beyond their thresholds still cause alarm flags to be set and alarm behaves according to the comparator/interrupt mode). alm_clmp1/alm_clmp0 = 10 this mode provides fully automatic clamping. prior to an alarm condition, the gate_ voltage is controlled by the sense voltage (max11014) or the dac setting (max11015). when an alarm condition triggers, the gate_ voltage clamps to aclamp_. the clamp is applied as long as the alarm condition is valid. the gate_ clamp is released when a subsequent adc conversion clears the alarm condition. the gate_ voltage is then restored to the sense voltage/dac set- ting. configure the alarm output in comparator mode to assert when the gate_ clamp is active. high threshold register voltage or temperature measurement value alarm comparator (active-low) time alarm interrupt (active-low) read alarm flag register read alarm flag register low threshold register figure 27. alarm hysteresis-mode timing example
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 58 ______________________________________________________________________________________ for a gate_ voltage alarm condition, gate_ remains clamped and alm_clmp 10 mode functions the same as 11 mode. this exception breaks the feedback loop that would have otherwise been created by sampling the gate_ voltage and then clamping that same voltage. alm_clmp1/alm_clmp0 = 11 this mode provides semi-automatic clamping. prior to an alarm condition, the gate_ voltage is controlled by the sense voltage (max11014) or the dac setting (max11015). when an alarm condition is triggered, the gate_ voltage clamps to aclamp_. the clamp holds the gate_ output in this condition, even if sub- sequent adc samples are taken and all alarm channels are cleared. to release the clamp, rewrite the alm_clmp1/alm_clmp0 bits to 11 or 01. opsafe inputs set the opsafe1 and opsafe2 inputs high to clamp the gate1 and gate2 outputs to the externally applied voltage at aclamp1 and aclamp2, respectively. opsafe1/opsafe2 override any software commands. the alm_clmp1/alm_clmp0 bits in the hardware alarm configuration register also provide clamping functionality. sram luts the max11014/max11015 implement four independent lookup tables (luts). the luts are temperature based (tlut) and numeric based (klut). channel 1 and channel 2 each have a separate t and k lut. each lut can store up to 48 separate data words. see figure 28. in addition to storing data values, the lut memory also contains configuration registers that spec- ify lut size, hysteresis bit value, and step size. table 28 details how the luts are configured in memory. write data to the luts with the following sequence: 1) write to the lut address register to set the base address for the first data word (the lutword bits are don? care in lut writes). 2) write to the lut data register to write data values. each time the lut data register is written, the address in the lut memory space is automatically incremented. read data from the luts with the following sequence: 1) write to the lut address register to set the base address for the first data word and the number of lut words to be read. 2) issue a single read command of the lut data reg- ister. the max11014/max11015 then fill the fifo with the requested lut data, starting with the data at the lutadd base address and incrementing until reaching either the top of memory or the num- ber of locations based on the lutword code. 3) read each of the 16-bit lut data words (including the 3- or 4-bit channel tag) from the fifo at dout in spi mode and sda in i 2 c mode. begin a lut write or read command by writing to the lut address register. see table 23. this register sets the lut base address and the number of lut locations to be read in a subsequent read of the lut data regis- ter. set the command byte to 7ah to write to the lut address register. set the lutword bits, d15?8, to the number of lut words (1 to 48) to be output during a lut read operation. set the lutadd bits, d7?0, to point to the base address of the lut data. the tlut1-0 to tlut1-47 (channel 1) values are stored at addresses 00h to 2fh. the tlut2-0 to tlut2-47 (channel 2) values are stored at addresses 30h to 5fh. the klut1-0 to klut1-47 (channel 1) values are stored at addresses 60h to 8fh. the klut2-0 to klut2-47 (channel 2) values are stored at addresses 90h to bfh. the luts are defined by setting the following parameters: 1) the table? base value 2) the step size of the table (how far apart the entries are) 3) the hysteresis threshold size 4) the size of the lut (the number of entries) lut configuration write a lut configuration sequence to initialize the step size, hysteresis threshold size, and size of the lut. determine the respective channel? temperature or k lut configuration with the following sequence: 1) set the lutadd bits in the lut address register to c0h (tlut1), c1h (tlut2), c2h (klut1) or c3h (klut2). see table 28a. 2) write to the lut data register (lutdat15?utdat0) to initialize the step size, hysteresis threshold size, and size of the lut. see table 28b.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 59 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 klut2base 0xc7 klut1base 0xc6 tlut2base 0xc5 tlut1base 0xc4 klut2cnfg 0xc3 0xc2 tlut2cnfg 0xc1 tlut1cnfg 0xc0 klut2 value 48 0xbf klut2 value 47 0xbe klut2 value 1 klut2 value 0 klut1 value 47 klut1 value 46 klut1 value 1 klut1 value 0 tlut2 value 47 tlut2 value 46 tlut2 value 1 tlut2 value 0 tlut1 value 47 tlut1 value 46 0x31 0x30 0x2f 0x2e hard address value 0x61 0x60 0x5f 0x5e hard address value 0x91 0x90 0x8f 0x8e hard address value hard address value hard address value hard address value hard address value hard address value hard address value hard address value hard address value tlut1 value 1 tlut1 value 0 klut1cnfg 0x00 hard address value 0x01 registers sram figure 28. lut memory space
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 60 ______________________________________________________________________________________ when performing a write operation, the first 3 lutdat bits, d15, d14, and d13 are don? care. when perform- ing a read operation, these bits are set to the lut data channel tag 110. bits d12?7 set the size of the lut in binary format. set the lut size between 8 (001000) and 48 (110000). bits d6, d5, and d4 set the hysteresis bit threshold. using the temperature lut as an exam- ple, if the hys value is 101 (16 bits) and the latest tem- perature measurement differs from the last one by more than 2?, a new tlut operation is performed and a new tlut value is calculated. bits d3?0 set the lut step size. see table 28c. the step size is based on the value of 2 n , with n equaling the digital value of the step bits. set the step size between 1 (2 0 ) and 512 (2 9 ). locations 1010 (2 10 ) to 1111 (2 15 ) are reserved. do not write to these locations. lut base the following two-step sequence determines the respective channel? temperature or k lut base value: 1) set the lutadd bits in the lut address register to c4h (tlut1), c5h (tlut2), c6h (klut1) and c7h (klut2). see table 28d. 2) write to the lut data register (lutdat15 lutdat0) to initialize the base word. the klut base value is stored in binary format, with the lsb equaling 1. the tlut base value is stored in two?- complement format, with the lsb equaling +0.125?. lutadd7?utadd0 hex function 0000 0000 to 0010 1111 00 to 2f tlut1-0 to tlut1-47 0011 0000 to 0101 1111 30 to 5f tlut2-0 to tlut2-47 0110 0000 to 1000 1111 60 to 8f klut1-0 to klut1-47 1001 0000 to 1011 1111 90 to bf klut2-0 to klut2-47 1100 0000 c0 tlut1 configuration 1100 0001 c1 tlut2 configuration 1100 0010 c2 klut1 configuration 1100 0011 c3 klut2 configuration 1100 0100 c4 tlut1 base 1100 0101 c5 tlut2 base 1100 0110 c6 klut1 base 1100 0111 c7 klut2 base table 28. lut addresses lutdat15 lutdat0 address name lutadd7 lutadd0 (hex) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tlut1 00 to 2f 110x msb lsb tlut2 30 to 5f 110x msb lsb klut1 60 to 8f 110x msb lsb klut2 90 to bf 110x msb lsb tlut1 configuration c0 1 1 0 see table 28b for bit details. tlut2 configuration c1 1 1 0 see table 28b for bit details. klut1 configuration c2 1 1 0 see table 28b for bit details. klut2 configuration c3 1 1 0 see table 28b for bit details. tlut1 base c4 1 1 0 x msb lsb tlut2 base c5 1 1 0 x msb lsb klut1 base c6 1 1 0 x msb lsb klut2 base c7 1 1 0 x msb lsb table 28a. lut data register memory map x = don? care.
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 61 bit name data bit reset function size5 d12 0 size4 d11 0 size3 d10 0 size2 d9 0 size1 d8 0 size0 d7 0 the size field is a straight binary representation of the size of the respective lut. size5 is the msb of the 6 size bits. size0 is the lsb. set the size of the lut between eight entries (001000) and 48 entries (110000). hys2 d6 0 hys1 d5 0 hys0 d4 0 the hys2, hys1, and hys0 bits set the hysteresis bit threshold for each lut. when the difference between the last index value and the next index value is less than the value set by hys2, hys1, and hys0 bits, the lut operation for that parameter is omitted and the last value calculated for the respective lut is used. set the hys2 (msb), hys1, and hys0 (lsb) bits to the following hysteresis bit values: 000: 0 bits (a new lut operation is always performed) 001: 1 bit (if the value differs by 1 bit, a new lut operation is performed) 010: 2 bits 011: 4 bits 100: 8 bits 101: 16 bits 110: 32 bits 111: 64 bits step3 d3 0 step2 d2 0 step1 d1 0 step0 d0 0 the step3?tep0 bits determine the lut 12-bit step size. the step size is a 2 n value. the n value is determined by the step bits, with step3 being the msb and step0 the lsb. see table 28c for the tlut and klut step-size equivalents. table 28b. lut configuration step3 step2 step1 step0 lut step size tlut step-size equivalent klut step-size equivalent 0 0 0 0 1 +0.125? 1 0 0 0 1 2 +0.25? 2 0 0 1 0 4 +0.5? 4 0 0 1 1 8 +1? 8 0 1 0 0 16 +2? 16 0 1 0 1 32 +4? 32 0 1 1 0 64 +8? 64 0 1 1 1 128 +16? 128 1 0 0 0 256 +32? 256 1 0 0 1 512 +64? 512 1 0 1 0 reserved. do not use. 1 0 1 1 reserved. do not use. 1 1 0 0 reserved. do not use. 1 1 0 1 reserved. do not use. 1 1 1 0 reserved. do not use. 1 1 1 1 reserved. do not use. table 28c. lut configuration step sizes
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 62 ______________________________________________________________________________________ both the t and k luts contain 12-bit data. the tlut data is stored in two?-complement format with decimal values ranging from -2048/2048 (-1) to +2047/2048 (+0.9995) in steps of approximately 0.0005. the klut data is stored in binary format with decimal values ranging from 0 to +4095/4096 (0.9998) in steps of approximately 0.0002. the temperature lut data is stored in two?-complement format. figure 29 details a channel 1 tlut example with eight entries where the base temperature is -30? and the step size is 128 (+16? between each entry). bit name data bit reset state function base11?ase0 d11?0 n/a the base value signifies the starting point for the lut. the klut base value is stored in binary format, with the lsb equaling 1. the tlut base value is stored in two?-complement format, with the lsb equaling +0.125?. table 28d. lut base klut2cnfg 0xc3 klut1cnfg 0xc2 tlut2cnfg 0xc1 t lut1cnfg = 0 0100 0xxx 0111 0xc0 0x00 tlut1 value 1 tlut1 value 0 0x01 tlut1 value 3 tlut1 value 2 tlut1 value 5 tlut1 value 4 tlut1 value 7 tlut1 value 6 tlut1 value 8 = unused 0x02 0x03 0x04 0x05 0x06 0x07 0x08 tlut1 base = -30 c klut2base 0xc7 klut1base 0xc6 tlut2base 0xc5 tlut1base = 1111 0001 0000 (-30?c) 0xc4 -14 c +2 c +18 c +34 c +50 c +66 c +82 c figure 29. tlut example
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 63 the klut data is stored in straight binary format. figure 30 details a channel 1 klut example with nine entries, a range of 0.5v to 1.7v, and a step size of 256. assuming v refdac = +2.5v, the base value (819d) is determined by the following equation: internally timed acquisitions and conversions clock mode 00 in clock mode 00, power-up, acquisition, conversion, and power-down are all initiated by writing to the adc conversion register and performed automatically using the internal oscillator. this is the default clock mode. with adcmon set to 1, the adc sets the busy output high, powers up, scans all requested channels, stores the results in the fifo, and then powers down. after the scan is complete, the busy output is pulled low and the results are available in the fifo. 05 25 4096 819 . . v v xd = klut2cnfg 0xc3 klut1cnfg = 0 0100 1xxx 1000 0xc2 tlut2cnfg 0xc1 t lut1cnfg 0xc0 0x60 klut1 value 1 klut1 value 0 0x61 klut1 value 3 klut1 value 2 klut1 value 5 klut1 value 4 klut1 value 7 klut1 value 6 klut1 value 8 0x62 0x63 0x64 0x65 0x66 0x67 0x68 klut1 base = 0.4999v klut2base 0xc7 klut1base = 0011 0011 0011 (819d) 0xc6 tlut2base 0xc5 tlut1base 0xc4 0.6561v 0.8124v 0.9686v 1.1249v 1.2811v 1.4374v 1.5936v 1.7499v klut1 value 9 = unused figure 30. klut example
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 64 ______________________________________________________________________________________ clock mode 01 in clock mode 01, power-up, acquisition, conversion, and power-down are all initiated by a single cnvst low pulse and performed automatically using the internal oscillator. initiate a scan by writing to the adc conver- sion register to indicate which channels to convert. then set cnvst low for at least 20ns only once to con- vert all of the channels selected in the adc conversion register. with adcmon set to 1, the adc sets the busy output high, powers up, scans all requested channels, stores the results in the fifo, and powers down. after the scan is complete, the busy output is pulled low and the results are available in the fifo. externally timed acquisitions and conversions clock mode 10 clock mode 10 is reserved. do not use this clock mode. clock mode 11 in clock mode 11, conversions are initiated by cnvst one at a time and performed using the internal oscilla- tor. see figures 31 and 32 for a pair of clock mode 11 timing examples. initiate a conversion by writing to the adc conversion register and pulling cnvst low for at least 1.5? for each channel converted. different timing parameters apply to whether the conversion is a tem- perature, a voltage using the external reference, or a voltage using the internal reference conversion. internal and external temperature conversions are inter- nally timed. set cnvst low for at least 20ns to acquire a temperature conversion. the busy output goes high while sampling and the internal reference typically requires 45? to power up. the temperature sensor cir- cuit requires 5? to power up. temperature conversion results are available after an additional 30?. the typi- cal conversion time of the initial temperature sensor scan is 80?. subsequent temperature scans only take 30? typically as the internal reference and tempera- ture sensor circuits are already powered. see the electrical characteristics table for more details. set cnvst low for at least 1.5? to acquire a voltage conversion using the external reference. the busy out- put goes high while sampling and the conversion results are available after an additional 3.5? (typ). set cnvst low for at least 50? to trigger an initial volt- age conversion using the internal reference. the busy output goes high and the conversion results are avail- able after an additional 3.5? typically. additional volt- age conversions do not require the acquisition time of powering up the internal reference. set cnvst low for at least 1.5? to power up the adc and place it in track mode. the busy output goes high while sampling and the conversion results are available after 5.6?. busy write to the adc conversion register to set up the scan ch0 (internal temperature) result loaded into the fifo clock mode 11 example 1: command a scan of channels 0, 5, and 10 with an internal reference. internally* int reference powers up in 45 s temp sensor powers up, acquires in 5 s temp conversion in 30 s idle, but reference and temperature sensor stay powered up 1.5 s acquisition for ch5 1.5 s acquisition for ch10 3.5 s conversion time for ch5 3.5 s conversion time for ch10 idle, but reference and temperature sensor stay powered up end of scan, reference and temperature sensor power down automatically ch5 loaded into the fifo ch10 loaded into the fifo t cnv11 t acq11 t acq11 *all timing specifications are typical. cnvst figure 31. clock mode 11 timing example 1
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 65 changing clock modes during adc conversions if the hardware configuration register? cksel1 or cksel0 bits are changed while the adc is performing a conversion (or series of conversions), the max11014/max11015 reacts in one of three ways: cksel1/cksel0 = 00 and is then changed to another value: the adc completes the already triggered series of conversions and then goes idle. the busy output remains high until the conversions are completed. the max11014/max11015 then responds according to commands with the new clock mode. cksel1/cksel0 = 01 and is then changed to another value: if waiting for the initial external trigger, the max11014/max11015 immediately exit clock mode 01, power down the adc, and go idle. if a conversion sequence is in progress, that conver- sion is completed and then the adc goes idle. the busy output remains high until the conversions are completed. the max11014/max11015 then respond according to commands with the new clock mode. cksel1/cksel0 = 11 and is then changed to another value: if waiting for an external trigger, the max11014/ max11015 immediately exit clock mode 11, power down the adc, and go idle. the busy output stays low and waits for the external trigger. if a conversion sequence is in progress, that con- version is completed and then the adc goes idle. applications information layout considerations for the external temperature sensor to perform to spec- ifications, care must be taken to place the max11014/max11015 as close as is practical to the remote diode. traces of dxp_ and dxn_ should not be routed across noisy lines and buses. dxp_ and dxn_ routes should be guarded by ground traces on either sides and should be routed over a quiet ground plane. traces should be wide enough (> 10mm) to lower inductance, which tends to pick up radiated noise. busy cnvst write to the adc conversion register to set up the scan ch6 (external temperature) result loaded into the fifo clock mode timing example 2: commands a scan of channels 5, 6, and 10 with an internal reference. internally* int reference powers up in 45 s 1.5 s acquisition of ch5 temperature conversion in 30 s idle, but reference stays powered up 3.5 s conversion time for ch5 idle, but reference and temperature sensor stay powered up 1.5 s acquisition for ch10 3.5 s conversion time for ch10 end of scan, reference and temperature sensor power down automatically ch5 loaded into the fifo ch10 loaded into the fifo t puint t acq11 t cnv11 temp sensor powers up, acquires in 5 s *all timing specifications are typical. figure 32. clock mode 11 timing example 2
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 66 ______________________________________________________________________________________ definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. inl for the max11014/max11015 is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. adc offset error for an ideal converter, the first transition occurs at 0.5 lsb, above zero. offset error is the amount of deviation between the measured first transition point and the ideal first transition point. adc gain error when a positive full-scale voltage is applied to the con- verter inputs, the digital output is all ones (fffh). the transition from ffeh to fffh occurs at 1.5 lsb below full scale. gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed. dac offset error dac offset error is determined by loading a code of all zeros into the dac and measuring the analog output voltage. dac gain error dac gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all 1s into the dac. aperture jitter aperture jitter, t aj , is the statistical distribution of the variation in the sampling instant. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist fre- quency excluding the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist fre- quency excluding the fundamental and the dc offset: effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 6 are the amplitudes of the first five harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spectral component. thd x vvvvv v log = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 enob sinad ( . ) / . =? 176 602 sinad db x signal noise rms rms ( ) log ( / ) = 20 snr x n db (. . ) =+ 602 176
max11014/max11015 automatic rf mesfet amplifier drain-current controllers ______________________________________________________________________________________ 67 adc channel-to-channel crosstalk bias the on channel to midscale. apply a full-scale sine- wave test tone to all off channels. perform an fft on the on channel. adc channel-to-channel crosstalk is expressed in db as the amplitude of the fft spur at the frequency associated with the off channel test tone. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f 2 , are present at the inputs. the intermodulation prod- ucts are (f 1 ? 2 ), (2 x f 1 ), (2 x f 2 ), (2 x f 1 ? 2 ), (2 x f 2 f 1 ). the individual input tone levels are at -7dbfs. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. note that the track/hold (t/h) performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. dac digital feedthrough dac digital feedthrough is the amount of noise that appears on the dac output when the dac digital con- trol lines are toggled. adc power-supply rejection power-supply rejection is defined as the shift in offset error when the power supply is moved from the minimum operating voltage to the maximum operating voltage. dac power-supply rejection dac psr is the amount of change in the converter? value at full scale as the power-supply voltage changes from its nominal value. psr assumes the converter? linearity is unaffected by changes in the power-supply voltage. chip information process: bicmos top view max11014 max11015 tqfn 7mm x 7mm x 0.8mm 13 14 15 16 17 18 19 20 21 22 23 24 aclamp2 gate2 gatev ss n.c. aclamp1 gate1 filt1 filt2 filt3 filt4 pgaout1 pgaout2 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 sclk/scl n.c./a2 spi/i2c cs / a0 alarm cnvst dgnd dv dd busy opsafe2 opsafe1 n.c. agnd av dd refadc refdac dxp2 dxn2 dxp1 dxn1 adcin2 adcin1 dout/a1 din/sda 36 35 34 33 32 31 30 29 28 27 26 25 agnd av dd av ss n.c. n.c. rcs2+ rcs2- rcs1- rcs1+ n.c. n.c. n.c. pin configuration
max11014/max11015 automatic rf mesfet amplifier drain-current controllers 68 ______________________________________________________________________________________ typical operating circuit max11014 max11015 c sclk/scl refadc refdac av dd dv dd din/sda alarm dxp1 dxn1 dxp2 dxn2 rcs1+ rcs1- rcs2+ rcs2- gate1 gate2 drain supply drain supply rf output rf intput rf output rf intput opsafe1 opsafe2 busy dgnd cnvst +5v external reference +5v (at mesfet) (at mesfet) adcin1 adcin2 aclamp1 aclamp2 filt1 filt2 filt3 filt4 cs /a0 dout/a1 n.c./a2 +5v +5v -5v pgaout1 pgaout2 agnd av ss gatev ss spi/i2c
max11014/max11015 automatic rf mesfet amplifier drain-current controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 69 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. heslington package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k detail b e l l1 package outline 21-0144 2 1 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m package outline 21-0144 2 2 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m

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